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* Enhanced edge detection in DEPP

Updated the DEPP VHDL component with clearer comment annotations and modified edge detection logic for address and data enable signals. Additionally, refined the main state machine by explicitly adding states for edge waiting periods and defining behaviors for each state, specifically regarding the handling of output FIFO signals and cycle initiation. Updated the edge detection mechanism within the address and data processing workflows, improving cycle handling for idle, address, and data states to better signal the transitions and manage the bus as well as the request and write enable signals.

* Implement FIFO compatible interface and update waveforms

Enhanced DEPP documentation and diagrams to reflect a transition to FIFO compatible interfaces for data traffic efficiency. Updated waveforms depict the revised cycle timings for data/address commands and address acknowledgment, ensuring clarity on the implemented protocol changes.

* Refine DEPP VHDL port naming for clarity

Updated the DEPP VHDL entity's port naming convention to enhance readability and consistency across data and address lines. Introduced clear "Fifo" and "AddressOut" prefixes as per FIFO compatible interfaces, replacing generic data and address signal names. This renaming also strengthens the association between ports and their respective data flow. Additional changes include:
- Replaced 'DataAviable' with a negated 'DataInFifo_EmptyFlag' for immediate data availability check.
- Streamlined write enable signals alignment with the new naming convention.
- Redesigned read-enable logic to minimize latency in 'RequestActive' mode by directly relaying the 'DataInFifo_DataAviable' status.
- Simplified and restructured bus wait management states to reflect the updated port names and signal handling improvements.
- Removed obsolete comments and updated documentation to accurately reflect the current interface functionality and structure.

* Enhanced DEPP module docs and waveform references

- Updated the DEPP module documentation to improve clarity and readability.
- Refactoring included renaming of waveform files for consistency and eliminating unnecessary whitespace.
- Revised virtual bus interface descriptions for better accuracy and cleared up the ambiguity in port names and their corresponding descriptions.
- Streamlined the ports and signals tables to enhance document structure and coherence.
- Modified the state machine SVG file for an up-to-date representation of the module design.
- Integrated additional waveform diagrams to detail the EPP (Enhanced Parallel Port) bus cycles within the documentation.

* Optimized EPP state machine timing

Refactored the EPP (Enhanced Parallel Port) VHDL state machine to streamline the signal handling for different operating states. This optimization includes removing redundant assignments to the `DEPP_Wait` signal in intermediary states and ensuring it is only held high for a minimum of one cycle where necessary. These modifications enhance the clarity of state transitions and may improve the system's timing performance, particularly for the start of read, write, and address cycles.

Additionally, the documentation is updated to include measured data rates, aiding in setting performance expectations.

* Enhanced UCF readability and added LA constraints

Reformatted the pin constraints section in Nexys2Test.ucf to improve readability, adding descriptive comments for RST, DataOutFullFlag, and RequestFullFlag signals. Removed unnecessary net constraints related to DEPP interface signals. Extended the UCF to include configuration for the Logic Analyzer (LA), specifying appropriate locations and providing comments linking net names to their corresponding physical connectors.

* Refactor signal handling and add Logic Analyzer output

Updated the Nexys2Test VHDL entity to streamline signal handling and add support for a Logic Analyzer interface. Removed commented-out attributes for virtual bus and related signals, which simplifies the interface section. Introduced new outputs for the Logic Analyzer to monitor various signals such as address, data enable, write enable, and wait signals, which improves debug and testing capabilities. In the architecture, redundant process handling DEPP_Wait has been removed to reduce complexity, and DEPP_Bus is now directly assigned. Updated the main process to simplify LED assignments and fixed an incorrect value for DataInFifo_EmptyFlag, enhancing signal accuracy and conforming to expected logic levels. These changes contribute to a more maintainable and understandable codebase.

* Update EPP documentation with data rate and refreshed diagrams

- Added the measured data transfer rate to the DEPP documentation.
- Replaced EPP bus waveform diagrams with updated versions.
- Resized and restructured the DEPP FSM SVG for better legibility, including adjustments to cluster dimensions, node positions, edges, and transitions.
- Renamed waveform SVG files for a consistent naming convention.

* Added logic analyzer capture visuals for documentation

* Added MIT License and enhanced README for DEPP module

Implemented an MIT License file and updated the README to provide comprehensive documentation for the VHDL Module designed for the Digilent Asynchronous Parallel Port Interface. The README now includes an overview of the module's purpose, features such as the measured data rate, visual diagrams for bus cycles, a detailed port definition table, module dependencies, contribution guidelines, licensing information, and acknowledgments, improving clarity and usability for end-users and contributors.
Co-authored-by: Max P <Mail@MPassarello.de>
Co-committed-by: Max P <Mail@MPassarello.de>
This commit is contained in:
0xMax42
2024-03-08 23:52:17 +01:00
committed by maxp
parent e72c7e882b
commit 2b2fdd3867
21 changed files with 844 additions and 220 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
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@@ -1 +1,2 @@
build/ build/
copy.sh

21
LICENSE Normal file
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@@ -0,0 +1,21 @@
MIT License
Copyright (c) 2024 Maximilian Passarello
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

60
Makefile
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@@ -6,8 +6,18 @@
## worldwide. This software is distributed without any warranty. ## worldwide. This software is distributed without any warranty.
########################################################################### ###########################################################################
include project.cfg ###########################################################################
# Version
###########################################################################
Makefile_Version := 1.0.0
$(info ISE Makefile Version: $(Makefile_Version))
###########################################################################
# Include project configuration
###########################################################################
include project.cfg
########################################################################### ###########################################################################
# Default values # Default values
@@ -32,19 +42,21 @@ BITFILE ?= build/$(PROJECT).bit
COMMON_OPTS ?= -intstyle xflow COMMON_OPTS ?= -intstyle xflow
XST_OPTS ?= XST_OPTS ?=
NGDBUILD_OPTS ?= NGDBUILD_OPTS ?=
MAP_OPTS ?= MAP_OPTS ?= -detail
PAR_OPTS ?= PAR_OPTS ?=
BITGEN_OPTS ?= BITGEN_OPTS ?=
TRACE_OPTS ?= TRACE_OPTS ?= -v 3 -n 3
FUSE_OPTS ?= -incremental FUSE_OPTS ?= -incremental
PROGRAMMER ?= none PROGRAMMER ?= none
PROGRAMMER_PRE ?=
IMPACT_OPTS ?= -batch impact.cmd IMPACT_OPTS ?= -batch impact.cmd
DJTG_EXE ?= djtgcfg DJTG_EXE ?= djtgcfg
DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
DJTG_INDEX ?= 0 DJTG_INDEX ?= 0
DJTG_FLASH_INDEX ?= 1
XC3SPROG_EXE ?= xc3sprog XC3SPROG_EXE ?= xc3sprog
XC3SPROG_CABLE ?= none XC3SPROG_CABLE ?= none
@@ -76,6 +88,28 @@ RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
# isim executables don't work without this # isim executables don't work without this
export XILINX export XILINX
# Initialize the libs and paths variables for VHDL and Verilog sources
VHD_PATHS ?=
VHD_LIBS ?=
V_PATHS ?=
V_LIBS ?=
# Define a function to process source files
define process_sources
$(foreach src,$(1),\
$(eval lib_and_path=$(subst :, ,$(src))) \
$(eval libname=$(word 1,$(lib_and_path))) \
$(eval filepath=$(word 2,$(lib_and_path))) \
$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
$(eval $(2) += $(libname)) \
$(eval $(3) += $(filepath)) \
)
endef
# Run the function for VHDL sources
$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
# Run the function for Verilog sources
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
########################################################################### ###########################################################################
# Default build # Default build
@@ -90,8 +124,9 @@ build/$(PROJECT).prj: project.cfg
@echo "Updating $@" @echo "Updating $@"
@mkdir -p build @mkdir -p build
@rm -f $@ @rm -f $@
@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;) @$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;) @$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
build/$(PROJECT)_sim.prj: build/$(PROJECT).prj build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
@cp build/$(PROJECT).prj $@ @cp build/$(PROJECT).prj $@
@@ -113,7 +148,7 @@ build/$(PROJECT).scr: project.cfg
"-p $(TARGET_PART)" \ "-p $(TARGET_PART)" \
> build/$(PROJECT).scr > build/$(PROJECT).scr
$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr $(BITFILE): project.cfg $(V_PATHS) $(VHD_PATHS) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
@mkdir -p build @mkdir -p build
$(call RUN,xst) $(COMMON_OPTS) \ $(call RUN,xst) $(COMMON_OPTS) \
-ifn $(PROJECT).scr -ifn $(PROJECT).scr
@@ -153,7 +188,7 @@ trace: project.cfg $(BITFILE)
test: $(TEST_EXES) test: $(TEST_EXES)
build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST) build/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) build/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \ $(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
-prj $(PROJECT)_sim.prj \ -prj $(PROJECT)_sim.prj \
-o isim_$*$(EXE) \ -o isim_$*$(EXE) \
@@ -176,17 +211,17 @@ isimgui: build/isim_$(TB)$(EXE)
ifeq ($(PROGRAMMER), impact) ifeq ($(PROGRAMMER), impact)
prog: $(BITFILE) prog: $(BITFILE)
sudo $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS) $(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
endif endif
ifeq ($(PROGRAMMER), digilent) ifeq ($(PROGRAMMER), digilent)
prog: $(BITFILE) prog: $(BITFILE)
yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE) $(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
endif endif
ifeq ($(PROGRAMMER), xc3sprog) ifeq ($(PROGRAMMER), xc3sprog)
prog: $(BITFILE) prog: $(BITFILE)
sudo $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE) $(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
endif endif
ifeq ($(PROGRAMMER), none) ifeq ($(PROGRAMMER), none)
@@ -200,10 +235,7 @@ endif
ifeq ($(PROGRAMMER), digilent) ifeq ($(PROGRAMMER), digilent)
flash: $(BITFILE) flash: $(BITFILE)
yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE) $(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
endif endif
########################################################################### ###########################################################################
# vim: set filetype=make: #

59
README.md
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@@ -1,45 +1,52 @@
# English # VHDL Module for the Digilent Asynchronous Parallel Port Interface (DEPP)
## VHDL Project Template Using Xilinx Build Tools with Makefile ## Overview
Welcome to the VHDL Project Template repository. This project is designed to streamline your FPGA development process using the Xilinx ISE Build Tools, integrated with a convenient Makefile approach for building and synthesizing your VHDL designs. The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface for use with Digilent FPGA boards. It facilitates communication between a host computer and the FPGA via the Digilent Adept software, supporting operations such as address write, data write, and data read cycles.
### Using the Makefile ## Features
To use the Makefile for building your VHDL projects, ensure you have the Xilinx Build Tools installed on your system. The Makefile is specifically configured to work with these tools to automate the build process. - Designed for integration with Digilent FPGA boards.
- Supports data transfers with Digilent Adept software.
- Measured data rate of approximately 4.68 kByte/s.
For detailed instructions on how to use the Makefile, please refer to the following URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). This page contains comprehensive guidance on setup and usage to get you started quickly. ## Bus Cycles Visualized
### Directory Structure - EPP Address Write Cycle
![Waveform of the EPP Address Write Cycle](docs/DEPP/wavedrom_HWwR0.svg "EPP Address Write")
The project is organized into various subdirectories, each serving a specific role in the development process. For an explanation of the directory structure and the contents of each subdirectory, please refer to the `README.md` files located within the subdirectories. These documents provide valuable insights into how the project is organized and how to navigate the files and folders efficiently. - EPP Data Write Cycle
![Waveform of the EPP Data Write Cycle](docs/DEPP/wavedrom_ypdi1.svg "EPP Data Write")
### Getting Started - EPP Data Read Cycle
![Waveform of the EPP Data Read Cycle](docs/DEPP/wavedrom_91sO2.svg "EPP Data Read")
To begin using this VHDL Project Template, clone the repository to your local machine and follow the instructions provided in the subdirectory `README.md` files to understand the project layout. Then, head over to the URL mentioned above for details on using the Makefile with the Xilinx Build Tools. ## Port Definitions
Thank you for choosing this VHDL Project Template. We hope it accelerates your development process and helps you achieve your project goals efficiently. | Port Name | Direction | Type | Description |
| ---------------- | --------- | ----------- | -------------------------------------------------- |
| CLK | in | std_logic | Clock signal. Rising edge triggered. |
| CE | in | std_logic | Chip enable. `1` = enabled, `0` = disabled. |
| RST | in | std_logic | Reset signal. `1` = reset, `0` = normal operation. |
| EPP-Interface | out | Virtual bus | EPP Interface for address and data operations. |
| FIFO-Data-Out | out | Virtual bus | FIFO compatible data and address output interface. |
| FIFO-Data-In | in | Virtual bus | FIFO compatible data input interface. |
| FIFO-Address-Out | out | Virtual bus | FIFO compatible request address output interface. |
--- Detailed information on virtual bus port configurations can be found within the [module's documentation](docs/DEPP/DEPP.md).
# Deutsch ## Dependencies
## VHDL-Projektvorlage unter Verwendung von Xilinx Build Tools mit Makefile The module depends on standard logic and numeric libraries available in VHDL. Ensure you have the latest version of the Digilent Adept software for proper interfacing with the module.
Willkommen im Repository der VHDL-Projektvorlage. Dieses Projekt wurde entwickelt, um Ihren FPGA-Entwicklungsprozess mit den Xilinx ISE Build Tools zu vereinfachen, integriert mit einem praktischen Makefile-Ansatz zum Bauen und Synthetisieren Ihrer VHDL-Designs. ## Contributing
### Verwendung des Makefiles Contributions to improve the module or extend its capabilities are welcome. Please adhere to the existing coding standards and provide documentation for any changes made.
Um das Makefile für den Bau Ihrer VHDL-Projekte zu verwenden, stellen Sie sicher, dass die Xilinx Build Tools auf Ihrem System installiert sind. Das Makefile ist speziell so konfiguriert, dass es mit diesen Tools arbeitet, um den Bauprozess zu automatisieren. ## License
Für detaillierte Anweisungen zur Verwendung des Makefiles besuchen Sie bitte die folgende URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). Diese Seite enthält umfassende Anleitungen zur Einrichtung und Verwendung, damit Sie schnell starten können. This module is open source and is distributed under the MIT license. Please see the [LICENSE](LICENSE) file for full details.
### Verzeichnisstruktur ## Acknowledgments
Das Projekt ist in verschiedene Unterverzeichnisse organisiert, von denen jedes eine spezifische Rolle im Entwicklungsprozess spielt. Für eine Erklärung der Verzeichnisstruktur und des Inhalts jedes Unterverzeichnisses beachten Sie bitte die `README.md`-Dateien, die sich in den Unterverzeichnissen befinden. Diese Dokumente bieten wertvolle Einblicke, wie das Projekt organisiert ist und wie Sie effizient durch die Dateien und Ordner navigieren. Special thanks to the Digilent team for providing a reference manual in which the diagrams and the description in the text are contradictory ;-)
### Erste Schritte
Um mit dieser VHDL-Projektvorlage zu beginnen, klonen Sie das Repository auf Ihre lokale Maschine und folgen Sie den Anweisungen in den `README.md`-Dateien der Unterverzeichnisse, um das Layout des Projekts zu verstehen. Anschließend besuchen Sie die oben genannte URL für Details zur Verwendung des Makefiles mit den Xilinx Build Tools.
Vielen Dank, dass Sie sich für diese VHDL-Projektvorlage entschieden haben. Wir hoffen, dass sie Ihren Entwicklungsprozess beschleunigt und Ihnen hilft, Ihre Projektziele effizient zu erreichen.

36
code/DEPP.ucf
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@@ -1,36 +0,0 @@
NET CLK LOC = B8;
NET CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
NET "Dout<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "Dout<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "Dout<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "Dout<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
NET "Dout<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
NET "Dout<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
NET "Dout<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
NET "Dout<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
NET "Din<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "Din<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "Din<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "Din<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "Din<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "Din<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "Din<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
NET "Din<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT,
NET "DEPP_AddressEnable" LOC = "V14" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "DEPP_DataEnable" LOC = "U14" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "DEPP_WriteEnable" LOC = "V16";
NET "DEPP_Wait" LOC = "N9";
NET "DEPP_Bus<0>" LOC = "R14";
NET "DEPP_Bus<1>" LOC = "R13";
NET "DEPP_Bus<2>" LOC = "P13";
NET "DEPP_Bus<3>" LOC = "T12";
NET "DEPP_Bus<4>" LOC = "N11";
NET "DEPP_Bus<5>" LOC = "R11";
NET "DEPP_Bus<6>" LOC = "P10";
NET "DEPP_Bus<7>" LOC = "R10";

354
code/DEPP.vhd
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@@ -1,13 +1,18 @@
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- @name Digilent EPP Interface -- @name Digilent EPP Interface
-- @version 0.3.0 -- @version 0.3.1
-- @author Maximilian Passarello (mpassarello.de) -- @author Maximilian Passarello (mpassarello.de)
--@ An EPP interface for Digilent FPGA boards --@ An EPP interface for Digilent FPGA boards
--@ This interface is designed to be used with the Digilent EPP interface --@ This interface is designed to be used with the Digilent EPP interface
--@ and the Digilent Adept software. --@ and the Digilent Adept software.
--@
--@ **Measured data rate ≈ 4.68 kByte/s**
--@
--@ Below are diagrams of the EPP bus:
-- @history -- @history
-- - 0.2.0 (2010.05.30) Initial version -- - 0.2.0 (2010.05.30) Initial version
-- - 0.3.0 (2024.03.06) Refactored and commented -- - 0.3.0 (2024.03.06) Refactored and commented
-- - 0.3.1 (2024.03.07) TODO
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Timing Diagram's -- Timing Diagram's
-- EPP Address Write -- EPP Address Write
@@ -29,16 +34,52 @@
--@ }, --@ },
--@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"] --@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
--@ } --@ }
-- EPP Data Write
--@ {
--@ "signal": [
--@ { "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Data"] },
--@ { "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
--@ { "node": "...A...B", "phase": 0.15 },
--@ { "name": "DEPP_DataEnable", "wave": "1..0...1.." },
--@ { "node": "...E.F.H.I", "phase": 0.15 },
--@ { "node": ".C.D.G", "phase": 0.15 },
--@ { "name": "DEPP_Wait", "wave": "x0...1...0" }
--@ ],
--@ "head": {
--@ "text": "EPP Data Write"
--@ },
--@ "foot": {
--@ "text": "EPP Data Write Cycle Timing Diagram"
--@ },
--@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
--@ }
-- EPP Data Read
--@ {
--@ "signal": [
--@ { "name": "DEPP_Bus", "wave": "zz...3...x", "data": ["Data"] },
--@ { "node": "...J.K.L.M", "phase": 0.15 },
--@ { "name": "DEPP_WriteEnable", "wave": "x1........" },
--@ { "node": "...A...B", "phase": 0.15 },
--@ { "name": "DEPP_DataEnable", "wave": "1..0...1.." },
--@ { "node": "...E..FH.I", "phase": 0.15 },
--@ { "node": ".C.D.G", "phase": 0.15 },
--@ { "name": "DEPP_Wait", "wave": "x0....1..0" }
--@ ],
--@ "head": {
--@ "text": "EPP Data Read"
--@ },
--@ "foot": {
--@ "text": "EPP Data Read Cycle Timing Diagram"
--@ },
--@ "edge": ["A+B min. 80 ns", "C+D min. 40 ns", "E+F 0 to 10 ms", "H+I 0 to 10 ms", "J+K max. 20 ns", "L+M min. 20 ns"
--@ ]
--@ }
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
entity DEPP is entity DEPP is
generic (
--@ Number of 8-bit registers
--@ `DOut` and `DIn` are 8 times this width
RegisterQuant : integer := 1
);
port ( port (
--@ Clock signal --@ Clock signal
--@ Rising edge triggered --@ Rising edge triggered
@@ -49,102 +90,267 @@ entity DEPP is
--@ Reset signal --@ Reset signal
--@ `1` = reset, `0` = normal operation --@ `1` = reset, `0` = normal operation
RST : in std_logic; RST : in std_logic;
--@ @virtualbus EPP-Interface EPP Interface --@ @virtualbus EPP-Interface @dir out EPP Interface
--@ Address strobe --@ Address strobe
DEPP_AddressEnable : in std_logic; DEPP_AddressEnable : in std_logic;
--@ Data strobe --@ Data strobe
DEPP_DataEnable : in std_logic; DEPP_DataEnable : in std_logic;
--@ Transfer direction control --@ Transfer direction control
--@ `1` = read (Host from DEPP), `0` = write (Host to DEPP) --@
--@ `1` = read (Host from DEPP);
--@ `0` = write (Host to DEPP)
DEPP_WriteEnable : in std_logic; DEPP_WriteEnable : in std_logic;
--@ Handshake signal --@ Handshake signal
--@ : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length --@
DEPP_Wait : out std_logic; --@ `0` = ready for new cycle;
--@ Data/Adress bus --@ `1` = closing current cycle and not ready for new cycle
--@
--@ Keep the signal low to delay the cycle length
DEPP_Wait : out std_logic := '1';
--@ Data/Adress bus;
--@ Tri-state
DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z'); DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z');
--@ @end --@ @end
--@ Data output --@ @virtualbus FIFO-Data-Out @dir out Data & Address Output. FIFO compatible interface
DOut : out std_logic_vector((RegisterQuant * 8) - 1 downto 0); --@ Data output corosponding to the address
DataOutFifo_Data : out std_logic_vector(7 downto 0);
--@ Address output
DataOutFifo_Address : out std_logic_vector(7 downto 0);
--@ Valid data & adress output if `1`. Is only 1 cycle valid
DataOutFifo_WriteEnable : out std_logic;
--@ If `1` the module delays the bus
--@ and dont rise the `WriteEnable` signal
DataOutFifo_FullFlag : in std_logic;
--@ @end
--@ @virtualbus FIFO-Data-In Data input. FIFO compatible interface
--@ Data input --@ Data input
DIn : in std_logic_vector((RegisterQuant * 8) - 1 downto 0)); DataInFifo_Data : in std_logic_vector(7 downto 0);
--@ If the fifo is not empty, the module will read the data
DataInFifo_EmptyFlag : in std_logic;
--@ Is one cycle `1` to indicate that the data is read
DataInFifo_ReadEnable : out std_logic;
--@ @end
--@ @virtualbus FIFO-Address-Out @dir out Request address output. FIFO compatible interface
--@ Address output for read requests
AddressOutFifo_Data : out std_logic_vector(7 downto 0);
--@ Valid address output if `1`. Is only 1 cycle valid
AddressOutFifo_WriteEnable : out std_logic;
--@ If `1` the module delays the bus
--@ and dont rise the `RequestEnable` signal
AddressOutFifo_FullFlag : in std_logic
--@ @end
);
end DEPP; end DEPP;
architecture Behavioral of DEPP is architecture Behavioral of DEPP is
--@ Function to calculate the number of bits needed to address the `N` registers --@ Catch the address as long as the mode (read/write) has not yet been decided.
function min_bits_for_states(N : integer) return integer is signal TempAddressRegister : std_logic_vector(7 downto 0) := (others => '0');
begin
if (N <= 2) then
return 1;
else
if (N mod 2 = 0) then
return 1 + min_bits_for_states(N/2);
else
return 1 + min_bits_for_states((N + 1)/2);
end if;
end if;
end function min_bits_for_states;
type RegisterType is array(RegisterQuant - 1 downto 0) --@ Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal
of std_logic_vector(7 downto 0); signal EPP_AddressEnableShiftRegister : std_logic_vector(1 downto 0) := (others => '0');
--@ Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal
signal EPP_DataEnableShiftRegister : std_logic_vector(1 downto 0) := (others => '0');
signal RegistersIn : RegisterType; --@ The states of the main state machine
signal RegistersOut : RegisterType; type ModeType is (Idle, RequestActive, SetData, WriteActive, WaitForFallingDataEnable, WaitingForFallingAddressEnable, AdressActive);
--@ The current state of the main state machine
signal Mode : ModeType := Idle;
signal EPPDInternal : std_logic_vector(7 downto 0); --@ The output signals for the output data fifo
signal Adress : std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0); signal InterWriteEnableOut : std_logic := '0';
--@ The output signals for the output address fifo
signal Intern_CE : std_logic := '1'; signal InterRequestEnable : std_logic := '0';
signal Intern_RST : std_logic := '0'; --@ Intermediary signal to start the address write cycle
signal InterAddressEnable : std_logic := '0';
--@ Negated `DataInFifo_EmptyFlag` signal
signal DataInFifo_DataAviable : std_logic;
begin begin
DEPP_Wait <= '1' when DEPP_DataEnable = '0' or DEPP_AddressEnable = '0' else DataInFifo_DataAviable <= not DataInFifo_EmptyFlag;
'0'; DataOutFifo_WriteEnable <= InterWriteEnableOut;
AddressOutFifo_WriteEnable <= InterRequestEnable;
DEPP_Bus <= EPPDInternal when (DEPP_WriteEnable = '1') else --@ Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister`
"ZZZZZZZZ"; --@ for the rising/falling edge detection.
EPP_AddressEnableCatch : process (CLK)
DEPP_AddrIn : process (DEPP_AddressEnable)
begin
if rising_edge(DEPP_AddressEnable) then
if DEPP_WriteEnable = '0' then
Adress <= DEPP_Bus(min_bits_for_states(RegisterQuant) - 1 downto 0);
end if;
end if;
end process;
DEPP_DIn : process (DEPP_DataEnable)
begin
if rising_edge(DEPP_DataEnable) then
if DEPP_WriteEnable = '0' then
RegistersOut(to_integer(unsigned(Adress))) <= DEPP_Bus;
end if;
end if;
end process;
EPPDInternal <= RegistersIn(to_integer(unsigned(Adress)));
DOutRegister : process (CLK)
begin begin
if rising_edge(CLK) then if rising_edge(CLK) then
if Intern_RST = '1' then if RST = '1' then
DOut <= (others => '0'); EPP_AddressEnableShiftRegister <= (others => '0');
elsif Intern_CE = '1' then elsif CE = '1' then
for i in 0 to RegisterQuant - 1 loop EPP_AddressEnableShiftRegister <= EPP_AddressEnableShiftRegister(0) & DEPP_AddressEnable;
DOut(((i + 1) * 8) - 1 downto ((i) * 8)) <= RegistersOut(i);
end loop;
end if; end if;
end if; end if;
end process; end process;
DInRegister : process (CLK) --@ Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`.
--@ for the rising/falling edge detection.
EPP_DataEnableCatch : process (CLK)
begin begin
if rising_edge(CLK) then if rising_edge(CLK) then
if Intern_RST = '1' then if RST = '1' then
null; EPP_DataEnableShiftRegister <= (others => '0');
elsif Intern_CE = '1' then elsif CE = '1' then
for i in 0 to RegisterQuant - 1 loop EPP_DataEnableShiftRegister <= EPP_DataEnableShiftRegister(0) & DEPP_DataEnable;
RegistersIn(i) <= DIn(((i + 1) * 8) - 1 downto ((i) * 8)); end if;
end loop; end if;
end process;
--@ Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal
--@ if in the `RequestActive` mode: Minimize the latency of the data read.
DataInFIFOMinimizeLatency : process (Mode, DataInFifo_DataAviable)
begin
if Mode = RequestActive then
DataInFifo_ReadEnable <= DataInFifo_DataAviable;
else
DataInFifo_ReadEnable <= '0';
end if;
end process;
EPP_WaitManagement : process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
DEPP_Wait <= '1';
DEPP_Bus <= (others => 'Z');
Mode <= Idle;
elsif CE = '1' then
case Mode is
when Idle =>
--@ In idle state the module waits for the beginning of a new cycle
--@ like write address, write data or read data.
--@ A new cycle is signaled via the signals `InterRequestEnable`,
--@ `InterWriteEnableOut` and `InterAddressEnable` provided by the
--@ `EPP_AddressCatch`, `EPP_ReciveData` and `EPP_ReciveRequest` processes.
DEPP_Bus <= (others => 'Z');
--@ If the data or address output fifo is full the module signals the host to wait.
DEPP_Wait <= DataOutFifo_FullFlag or AddressOutFifo_FullFlag;
if InterRequestEnable = '1' then
--@ Start the read cycle
Mode <= RequestActive;
DEPP_Wait <= '0';
elsif InterWriteEnableOut = '1' then
--@ Start the write cycle
Mode <= WaitForFallingDataEnable;
elsif InterAddressEnable = '1' then
--@ Start the address write cycle
Mode <= WaitingForFallingAddressEnable;
end if;
when AdressActive =>
--@ Intermediary state to hold the `DEPP_Wait` minimum one cycle high.
Mode <= WaitingForFallingAddressEnable;
when WriteActive =>
--@ Intermediary state to hold the `DEPP_Wait` minimum one cycle high.
Mode <= WaitForFallingDataEnable;
when RequestActive =>
DEPP_Wait <= '0';
if DataInFifo_DataAviable = '1' then
Mode <= SetData;
end if;
when SetData =>
DEPP_Bus <= DataInFifo_Data;
Mode <= WaitForFallingDataEnable;
when WaitForFallingDataEnable =>
DEPP_Wait <= '1';
if EPP_DataEnableShiftRegister = "01" then
Mode <= Idle;
elsif (EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11") then
Mode <= Idle;
end if;
when WaitingForFallingAddressEnable =>
DEPP_Wait <= '1';
if EPP_AddressEnableShiftRegister = "01" then
Mode <= Idle;
elsif (EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11") then
Mode <= Idle;
end if;
when others =>
DEPP_Wait <= '1';
DEPP_Bus <= (others => 'Z');
Mode <= Idle;
end case;
end if;
end if;
end process;
--@ Address write cycle:
--@ If the `DEPP_AddressEnable` signal rises,
--@ he `DEPP_WriteEnable` signal is low and the module is in idle state
--@ the `DEPP_Bus` is stored in the `TempAddressRegister`.
EPP_AddressCatch : process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
TempAddressRegister <= (others => '0');
InterAddressEnable <= '0';
elsif CE = '1' then
-- Self reset the `InterAddressEnableRst` signal after one cycle high.
if InterAddressEnable = '1' then
InterAddressEnable <= '0';
end if;
if (EPP_AddressEnableShiftRegister = "10") and (DEPP_WriteEnable = '0') and (Mode = Idle) then
TempAddressRegister <= DEPP_Bus;
InterAddressEnable <= '1';
end if;
end if;
end if;
end process;
--@ Data write cycle:
--@ If the `DEPP_DataEnable` signal rises,
--@ the `DEPP_WriteEnable` signal is low
--@ and the module is in idle state
--@ the `DEPP_Bus` is stored in the `DataOut`,
--@ the `TempAddressRegister` is stored in the `AddressOut`
--@ and the `WriteEnableOut` signal is set to `1`.
EPP_ReciveData : process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
DataOutFifo_Address <= (others => '0');
DataOutFifo_Data <= (others => '0');
InterWriteEnableOut <= '0';
elsif CE = '1' then
-- Self reset the `WriteEnableOut` signal after one cycle high.
if InterWriteEnableOut = '1' then
InterWriteEnableOut <= '0';
end if;
if (EPP_DataEnableShiftRegister = "10") and (DEPP_WriteEnable = '0') and (Mode = Idle) then
DataOutFifo_Address <= TempAddressRegister;
DataOutFifo_Data <= DEPP_Bus;
InterWriteEnableOut <= '1';
end if;
end if;
end if;
end process;
--@ Data read cycle:
--@ If the `DEPP_DataEnable` signal rises,
--@ the `DEPP_WriteEnable` signal is high (read)
--@ and the module is in idle state
--@ the `TempAddressRegister` is stored in the `RequestAddress`
--@ and the `RequestEnable` signal is set to `1`.
EPP_ReciveRequest : process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
AddressOutFifo_Data <= (others => '0');
InterRequestEnable <= '0';
elsif CE = '1' then
-- Self reset the `RequestEnable` signal after one cycle high.
if InterRequestEnable = '1' then
InterRequestEnable <= '0';
end if;
if (EPP_DataEnableShiftRegister = "10") and (DEPP_WriteEnable = '1') and (Mode = Idle) then
AddressOutFifo_Data <= TempAddressRegister;
InterRequestEnable <= '1';
end if;
end if; end if;
end if; end if;
end process; end process;

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### Pin Constraints for the Nexys 2 Board ###
NET CLK LOC = B8;
NET CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
NET "RST" LOC = "B18"; # BTN0
NET "DataOutFullFlag" LOC = "D18"; # BTN1
NET "RequestFullFlag" LOC = "E18"; # BTN2
NET "LED<0>" LOC = "J14";
NET "LED<1>" LOC = "J15";
NET "LED<2>" LOC = "K15";
NET "LED<3>" LOC = "K14";
NET "LED<4>" LOC = "E16";
NET "LED<5>" LOC = "P16";
NET "LED<6>" LOC = "E4";
NET "LED<7>" LOC = "P4";
NET "Switches<0>" LOC = "G18";
NET "Switches<1>" LOC = "H18";
NET "Switches<2>" LOC = "K18";
NET "Switches<3>" LOC = "K17";
NET "Switches<4>" LOC = "L14";
NET "Switches<5>" LOC = "L13";
NET "Switches<6>" LOC = "N17";
NET "Switches<7>" LOC = "R17";
### ##################################### ###
### DEPP Interface ###
NET "DEPP_AddressEnable" LOC = "V14";
NET "DEPP_DataEnable" LOC = "U14";
NET "DEPP_WriteEnable" LOC = "V16";
NET "DEPP_Wait" LOC = "N9";
NET "DEPP_Bus<0>" LOC = "R14";
NET "DEPP_Bus<1>" LOC = "R13";
NET "DEPP_Bus<2>" LOC = "P13";
NET "DEPP_Bus<3>" LOC = "T12";
NET "DEPP_Bus<4>" LOC = "N11";
NET "DEPP_Bus<5>" LOC = "R11";
NET "DEPP_Bus<6>" LOC = "P10";
NET "DEPP_Bus<7>" LOC = "R10";
### ############## ###
### Logik Analyzer ###
NET "LA_AddressEnable" LOC = "L15"; # JA 0
NET "LA_DataEnable" LOC = "K12"; # JA 1
NET "LA_WriteEnable" LOC = "L17"; # JA 2
NET "LA_Wait" LOC = "M15"; # JA 3
NET "LA_Bus<0>" LOC = "M13"; # JB 0
NET "LA_Bus<1>" LOC = "R18"; # JB 1
NET "LA_Bus<2>" LOC = "R15"; # JB 2
NET "LA_Bus<3>" LOC = "T17"; # JB 3
NET "LA_Bus<4>" LOC = "P17"; # JB 4
NET "LA_Bus<5>" LOC = "R16"; # JB 5
NET "LA_Bus<6>" LOC = "T18"; # JB 6
NET "LA_Bus<7>" LOC = "U18"; # JB 7
### ############## ###

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Nexys2Test is
port (
CLK : in std_logic;
RST : in std_logic;
LED : out std_logic_vector(7 downto 0);
Switches : in std_logic_vector(7 downto 0);
DataOutFullFlag : in std_logic;
RequestFullFlag : in std_logic;
-- Logic Analyzer
LA_AddressEnable : out std_logic;
LA_DataEnable : out std_logic;
LA_WriteEnable : out std_logic;
LA_Wait : out std_logic;
LA_Bus : inout std_logic_vector(7 downto 0);
-- EPP Interface
DEPP_AddressEnable : in std_logic;
DEPP_DataEnable : in std_logic;
DEPP_WriteEnable : in std_logic;
DEPP_Wait : out std_logic;
DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z')
);
end Nexys2Test;
architecture Behavioral of Nexys2Test is
component DEPP
port (
CLK : in std_logic;
CE : in std_logic;
RST : in std_logic;
DEPP_AddressEnable : in std_logic;
DEPP_DataEnable : in std_logic;
DEPP_WriteEnable : in std_logic;
DEPP_Wait : out std_logic;
DEPP_Bus : inout std_logic_vector(7 downto 0);
DataOutFifo_Data : out std_logic_vector(7 downto 0);
DataOutFifo_Address : out std_logic_vector(7 downto 0);
DataOutFifo_WriteEnable : out std_logic;
DataOutFifo_FullFlag : in std_logic;
DataInFifo_Data : in std_logic_vector(7 downto 0);
DataInFifo_EmptyFlag : in std_logic;
DataInFifo_ReadEnable : out std_logic;
AddressOutFifo_Data : out std_logic_vector(7 downto 0);
AddressOutFifo_WriteEnable : out std_logic;
AddressOutFifo_FullFlag : in std_logic
);
end component;
signal InterLED : std_logic_vector(7 downto 0);
signal InterSwitches : std_logic_vector(7 downto 0);
signal DataAviable : std_logic;
signal InternWait : std_logic;
signal InternRST : std_logic;
signal EPP_Bus : std_logic_vector(7 downto 0);
begin
DEPP_inst : DEPP
port map(
CLK => CLK,
CE => '1',
RST => InternRST,
DEPP_AddressEnable => DEPP_AddressEnable,
DEPP_DataEnable => DEPP_DataEnable,
DEPP_WriteEnable => DEPP_WriteEnable,
DEPP_Wait => InternWait,
DEPP_Bus => EPP_Bus,
DataOutFifo_Data => InterLED,
DataOutFifo_Address => open,
DataOutFifo_WriteEnable => DataAviable,
DataOutFifo_FullFlag => DataOutFullFlag,
DataInFifo_Data => InterSwitches,
DataInFifo_EmptyFlag => '0',
DataInFifo_ReadEnable => open,
AddressOutFifo_Data => open,
AddressOutFifo_WriteEnable => open,
AddressOutFifo_FullFlag => RequestFullFlag
);
DEPP_Wait <= InternWait;
DEPP_Bus <= EPP_Bus;
LA_Bus <= EPP_Bus;
LA_AddressEnable <= DEPP_AddressEnable;
LA_DataEnable <= DEPP_DataEnable;
LA_WriteEnable <= DEPP_WriteEnable;
LA_Wait <= InternWait;
process (CLK)
begin
if rising_edge(CLK) then
LED <= InterLED;
InternRST <= RST;
InterSwitches <= Switches;
end if;
end process;
end Behavioral;

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# Entity: DEPP # Entity: DEPP
- **File**: DEPP.vhd - **File**: DEPP.vhd
## Diagram ## Diagram
![Diagram](DEPP.svg "Diagram")
![Module Diagram](DEPP.svg "DEPP Module")
## Description ## Description
An EPP interface for Digilent FPGA boards An EPP interface for Digilent FPGA boards
This interface is designed to be used with the Digilent EPP interface This interface is designed to be used with the Digilent EPP interface
and the Digilent Adept software. and the Digilent Adept software.
**Measured data rate ≈ 4.68 kByte/s**
Below are diagrams of the EPP bus:
![alt text](wavedrom_SDc50.svg "title") ![Waveform of the EPP Address Write Cycle](wavedrom_HWwR0.svg "EPP Address Write")
![Waveform of the EPP Data Write Cycle](wavedrom_ypdi1.svg "EPP Data Write")
![Waveform of the EPP Data Read Cycle](wavedrom_91sO2.svg "EPP Data Read")
## Generics
| Generic name | Type | Value | Description |
| ------------- | ------- | ----- | ------------------------------------------------------------------ |
| RegisterQuant | integer | 1 | Number of 8-bit registers `DOut` and `DIn` are 8 times this width |
## Ports ## Ports
| Port name | Direction | Type | Description | | Port name | Direction | Type | Description |
| ------------- | --------- | -------------------------------------------------- | ------------------------------------------------- | | ---------------- | --------- | ----------- | ------------------------------------------------- |
| CLK | in | std_logic | Clock signal Rising edge triggered | | CLK | in | std_logic | Clock signal Rising edge triggered |
| CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled | | CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled |
| RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation | | RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation |
| DOut | out | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data output | | EPP-Interface | out | Virtual bus | EPP Interface |
| DIn | in | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data input | | FIFO-Data-Out | out | Virtual bus | Data & Address Output. FIFO compatible interface |
| EPP-Interface | in | Virtual bus | EPP Interface | | FIFO-Data-In | in | Virtual bus | Data input. FIFO compatible interface |
| FIFO-Address-Out | out | Virtual bus | Request address output. FIFO compatible interface |
### Virtual Buses ### Virtual Buses
#### EPP-Interface #### EPP-Interface
| Port name | Direction | Type | Description | | Port name | Direction | Type | Description |
| ------------------ | --------- | ---------------------------- | ------------------------------------------------------------------------------------------------------------------------- | | ------------------ | --------- | ---------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------- |
| DEPP_AddressEnable | in | std_logic | Address strobe | | DEPP_AddressEnable | in | std_logic | Address strobe |
| DEPP_DataEnable | in | std_logic | Data strobe | | DEPP_DataEnable | in | std_logic | Data strobe |
| DEPP_WriteEnable | in | std_logic | Transfer direction control `1` = read (Host from DEPP), `0` = write (Host to DEPP) | | DEPP_WriteEnable | in | std_logic | Transfer direction control<br> `1` = read (Host from DEPP); `0` = write (Host to DEPP) |
| DEPP_Wait | out | std_logic | Handshake signal : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length | | DEPP_Wait | out | std_logic | Handshake signal <br> `0` = ready for new cycle; `1` = closing current cycle and not ready for new cycle<br> Keep the signal low to delay the cycle length |
| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus | | DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus; Tri-state |
#### FIFO-Data-Out
| Port name | Direction | Type | Description |
| ----------------------- | --------- | ---------------------------- | ----------------------------------------------------------------------- |
| DataOutFifo_Data | out | std_logic_vector(7 downto 0) | Data output corosponding to the address |
| DataOutFifo_Address | out | std_logic_vector(7 downto 0) | Address output |
| DataOutFifo_WriteEnable | out | std_logic | Valid data & adress output if `1`. Is only 1 cycle valid |
| DataOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `WriteEnable` signal |
#### FIFO-Data-In
| Port name | Direction | Type | Description |
| --------------------- | --------- | ---------------------------- | ------------------------------------------------------- |
| DataInFifo_Data | in | std_logic_vector(7 downto 0) | Data input |
| DataInFifo_EmptyFlag | in | std_logic | If the fifo is not empty, the module will read the data |
| DataInFifo_ReadEnable | out | std_logic | Is one cycle `1` to indicate that the data is read |
#### FIFO-Address-Out
| Port name | Direction | Type | Description |
| -------------------------- | --------- | ---------------------------- | ------------------------------------------------------------------------- |
| AddressOutFifo_Data | out | std_logic_vector(7 downto 0) | Address output for read requests |
| AddressOutFifo_WriteEnable | out | std_logic | Valid address output if `1`. Is only 1 cycle valid |
| AddressOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `RequestEnable` signal |
## Signals ## Signals
| Name | Type | Description | | Name | Type | Description |
| ------------ | ----------------------------------------------------------------- | ----------- | | ------------------------------ | ---------------------------- | --------------------------------------------------------------------------------------- |
| RegistersIn | RegisterType | | | TempAddressRegister | std_logic_vector(7 downto 0) | Catch the address as long as the mode (read/write) has not yet been decided. |
| RegistersOut | RegisterType | | | EPP_AddressEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal |
| EPPDInternal | std_logic_vector(7 downto 0) | | | EPP_DataEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal |
| Adress | std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0) | | | Mode | ModeType | The current state of the main state machine |
| Intern_CE | std_logic | | | InterWriteEnableOut | std_logic | The output signals for the output data fifo |
| Intern_RST | std_logic | | | InterRequestEnable | std_logic | The output signals for the output address fifo |
| InterAddressEnable | std_logic | Intermediary signal to start the address write cycle |
| DataInFifo_DataAviable | std_logic | Negated `DataInFifo_EmptyFlag` signal |
## Types ## Types
| Name | Type | Description | | Name | Type | Description |
| ------------ | ---- | ----------- | | -------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------ |
| RegisterType | | | | ModeType | (Idle,<br><span style="padding-left:20px"> RequestActive,<br><span style="padding-left:20px"> SetData,<br><span style="padding-left:20px"> WriteActive,<br><span style="padding-left:20px"> WaitForFallingDataEnable,<br><span style="padding-left:20px"> WaitingForFallingAddressEnable,<br><span style="padding-left:20px"> AdressActive) | The states of the main state machine |
## Functions
- min_bits_for_states <font id="function_arguments">(N : integer)</font> <font id="function_return">return integer</font>
- Function to calculate the number of bits needed to address the `N` registers
## Processes ## Processes
- DEPP_AddrIn: ( DEPP_AddressEnable )
- DEPP_DIn: ( DEPP_DataEnable ) - EPP_AddressEnableCatch: ( CLK )
- DOutRegister: ( CLK ) - **Description**
- DInRegister: ( CLK ) Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` for the rising/falling edge detection.
- EPP_DataEnableCatch: ( CLK )
- **Description**
Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`. for the rising/falling edge detection.
- DataInFIFOMinimizeLatency: ( Mode, DataInFifo_DataAviable )
- **Description**
Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal if in the `RequestActive` mode: Minimize the latency of the data read.
- EPP_WaitManagement: ( CLK )
- EPP_AddressCatch: ( CLK )
- **Description**
Address write cycle: If the `DEPP_AddressEnable` signal rises, he `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `TempAddressRegister`.
- EPP_ReciveData: ( CLK )
- **Description**
Data write cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `DataOut`, the `TempAddressRegister` is stored in the `AddressOut` and the `WriteEnableOut` signal is set to `1`.
- EPP_ReciveRequest: ( CLK )
- **Description**
Data read cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is high (read) and the module is in idle state the `TempAddressRegister` is stored in the `RequestAddress` and the `RequestEnable` signal is set to `1`.
## State machines
![Diagram_state_machine_0](fsm_DEPP_00.svg "Diagram")

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docs/Waveforms/EPP Address Write.json → docs/DEPP/Waveforms/EPP Address Write.json
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docs/DEPP/Waveforms/EPP Data Read.json Normal file
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"signal": [
{ "name": "DEPP_Bus", "wave": "zz...3...x", "data": ["Adress"] },
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"head": {
"text": "EPP Data Read"
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"text": "EPP Data Read Cycle Timing Diagram"
},
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]
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docs/DEPP/Waveforms/EPP Data Write.json Normal file
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{
"signal": [
{ "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Adress"] },
{ "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
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{ "name": "DEPP_Wait", "wave": "x0...1...0" }
],
"head": {
"text": "EPP Data Write"
},
"foot": {
"text": "EPP Data Write Cycle Timing Diagram"
},
"edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
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<title>AdressActive</title>
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8
project.cfg
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@@ -12,10 +12,10 @@ TARGET_PART = xc3s1200e-4-fg320
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
# Optional the name of the top module (default is the project name) # Optional the name of the top module (default is the project name)
# TOPLEVEL = TOPLEVEL = Nexys2Test
# Optional the name of the ucf file (default is the project name) # Optional the name of the ucf file (default is the project name)
CONSTRAINTS = code/DEPP.ucf CONSTRAINTS = code/Nexys2Test.ucf
## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
# --------------------- # ---------------------
@@ -25,6 +25,7 @@ CONSTRAINTS = code/DEPP.ucf
# @example `VSOURCE += src/main.v` (add a single Verilog file per line) # @example `VSOURCE += src/main.v` (add a single Verilog file per line)
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line) # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
VHDSOURCE += code/Nexys2Test.vhd
VHDSOURCE += code/DEPP.vhd VHDSOURCE += code/DEPP.vhd
## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
@@ -81,5 +82,8 @@ DJTG_INDEX = 0
# The index of the flash device for the `flash` target # The index of the flash device for the `flash` target
DJTG_FLASH_INDEX = 1 DJTG_FLASH_INDEX = 1
# Pre-programmer command
PROGRAMMER_PRE = yes Y | sudo
## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
# --------------------- # ---------------------