HDL/DEPP
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dev (#1)

Browse Source 
* Enhanced edge detection in DEPP

Updated the DEPP VHDL component with clearer comment annotations and modified edge detection logic for address and data enable signals. Additionally, refined the main state machine by explicitly adding states for edge waiting periods and defining behaviors for each state, specifically regarding the handling of output FIFO signals and cycle initiation. Updated the edge detection mechanism within the address and data processing workflows, improving cycle handling for idle, address, and data states to better signal the transitions and manage the bus as well as the request and write enable signals.

* Implement FIFO compatible interface and update waveforms

Enhanced DEPP documentation and diagrams to reflect a transition to FIFO compatible interfaces for data traffic efficiency. Updated waveforms depict the revised cycle timings for data/address commands and address acknowledgment, ensuring clarity on the implemented protocol changes.

* Refine DEPP VHDL port naming for clarity

Updated the DEPP VHDL entity's port naming convention to enhance readability and consistency across data and address lines. Introduced clear "Fifo" and "AddressOut" prefixes as per FIFO compatible interfaces, replacing generic data and address signal names. This renaming also strengthens the association between ports and their respective data flow. Additional changes include:
- Replaced 'DataAviable' with a negated 'DataInFifo_EmptyFlag' for immediate data availability check.
- Streamlined write enable signals alignment with the new naming convention.
- Redesigned read-enable logic to minimize latency in 'RequestActive' mode by directly relaying the 'DataInFifo_DataAviable' status.
- Simplified and restructured bus wait management states to reflect the updated port names and signal handling improvements.
- Removed obsolete comments and updated documentation to accurately reflect the current interface functionality and structure.

* Enhanced DEPP module docs and waveform references

- Updated the DEPP module documentation to improve clarity and readability.
- Refactoring included renaming of waveform files for consistency and eliminating unnecessary whitespace.
- Revised virtual bus interface descriptions for better accuracy and cleared up the ambiguity in port names and their corresponding descriptions.
- Streamlined the ports and signals tables to enhance document structure and coherence.
- Modified the state machine SVG file for an up-to-date representation of the module design.
- Integrated additional waveform diagrams to detail the EPP (Enhanced Parallel Port) bus cycles within the documentation.

* Optimized EPP state machine timing

Refactored the EPP (Enhanced Parallel Port) VHDL state machine to streamline the signal handling for different operating states. This optimization includes removing redundant assignments to the `DEPP_Wait` signal in intermediary states and ensuring it is only held high for a minimum of one cycle where necessary. These modifications enhance the clarity of state transitions and may improve the system's timing performance, particularly for the start of read, write, and address cycles.

Additionally, the documentation is updated to include measured data rates, aiding in setting performance expectations.

* Enhanced UCF readability and added LA constraints

Reformatted the pin constraints section in Nexys2Test.ucf to improve readability, adding descriptive comments for RST, DataOutFullFlag, and RequestFullFlag signals. Removed unnecessary net constraints related to DEPP interface signals. Extended the UCF to include configuration for the Logic Analyzer (LA), specifying appropriate locations and providing comments linking net names to their corresponding physical connectors.

* Refactor signal handling and add Logic Analyzer output

Updated the Nexys2Test VHDL entity to streamline signal handling and add support for a Logic Analyzer interface. Removed commented-out attributes for virtual bus and related signals, which simplifies the interface section. Introduced new outputs for the Logic Analyzer to monitor various signals such as address, data enable, write enable, and wait signals, which improves debug and testing capabilities. In the architecture, redundant process handling DEPP_Wait has been removed to reduce complexity, and DEPP_Bus is now directly assigned. Updated the main process to simplify LED assignments and fixed an incorrect value for DataInFifo_EmptyFlag, enhancing signal accuracy and conforming to expected logic levels. These changes contribute to a more maintainable and understandable codebase.

* Update EPP documentation with data rate and refreshed diagrams

- Added the measured data transfer rate to the DEPP documentation.
- Replaced EPP bus waveform diagrams with updated versions.
- Resized and restructured the DEPP FSM SVG for better legibility, including adjustments to cluster dimensions, node positions, edges, and transitions.
- Renamed waveform SVG files for a consistent naming convention.

* Added logic analyzer capture visuals for documentation

* Added MIT License and enhanced README for DEPP module

Implemented an MIT License file and updated the README to provide comprehensive documentation for the VHDL Module designed for the Digilent Asynchronous Parallel Port Interface. The README now includes an overview of the module's purpose, features such as the measured data rate, visual diagrams for bus cycles, a detailed port definition table, module dependencies, contribution guidelines, licensing information, and acknowledgments, improving clarity and usability for end-users and contributors.
Co-authored-by: Max P <Mail@MPassarello.de>
Co-committed-by: Max P <Mail@MPassarello.de>
This commit is contained in:
0xMax42
2024-03-08 23:52:17 +01:00
committed by maxp
parent e72c7e882b
commit 2b2fdd3867
21 changed files with 844 additions and 220 deletions
Download Patch File Download Diff File Expand all files Collapse all files

130
docs/DEPP/DEPP.md
View File

@@ -1,73 +1,117 @@
# Entity: DEPP
# Entity: DEPP
- **File**: DEPP.vhd
## Diagram
![Diagram](DEPP.svg "Diagram")
![Module Diagram](DEPP.svg "DEPP Module")
## Description
An EPP interface for Digilent FPGA boards
This interface is designed to be used with the Digilent EPP interface
and the Digilent Adept software.
**Measured data rate ≈ 4.68 kByte/s**
Below are diagrams of the EPP bus:
![alt text](wavedrom_SDc50.svg "title")
![Waveform of the EPP Address Write Cycle](wavedrom_HWwR0.svg "EPP Address Write")
![Waveform of the EPP Data Write Cycle](wavedrom_ypdi1.svg "EPP Data Write")
## Generics
| Generic name | Type | Value | Description |
| ------------- | ------- | ----- | ------------------------------------------------------------------ |
| RegisterQuant | integer | 1 | Number of 8-bit registers `DOut` and `DIn` are 8 times this width |
![Waveform of the EPP Data Read Cycle](wavedrom_91sO2.svg "EPP Data Read")
## Ports
| Port name | Direction | Type | Description |
| ------------- | --------- | -------------------------------------------------- | ------------------------------------------------- |
| CLK | in | std_logic | Clock signal Rising edge triggered |
| CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled |
| RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation |
| DOut | out | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data output |
| DIn | in | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data input |
| EPP-Interface | in | Virtual bus | EPP Interface |
| Port name | Direction | Type | Description |
| ---------------- | --------- | ----------- | ------------------------------------------------- |
| CLK | in | std_logic | Clock signal Rising edge triggered |
| CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled |
| RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation |
| EPP-Interface | out | Virtual bus | EPP Interface |
| FIFO-Data-Out | out | Virtual bus | Data & Address Output. FIFO compatible interface |
| FIFO-Data-In | in | Virtual bus | Data input. FIFO compatible interface |
| FIFO-Address-Out | out | Virtual bus | Request address output. FIFO compatible interface |
### Virtual Buses
#### EPP-Interface
| Port name | Direction | Type | Description |
| ------------------ | --------- | ---------------------------- | ------------------------------------------------------------------------------------------------------------------------- |
| DEPP_AddressEnable | in | std_logic | Address strobe |
| DEPP_DataEnable | in | std_logic | Data strobe |
| DEPP_WriteEnable | in | std_logic | Transfer direction control `1` = read (Host from DEPP), `0` = write (Host to DEPP) |
| DEPP_Wait | out | std_logic | Handshake signal : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length |
| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus |
| Port name | Direction | Type | Description |
| ------------------ | --------- | ---------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------- |
| DEPP_AddressEnable | in | std_logic | Address strobe |
| DEPP_DataEnable | in | std_logic | Data strobe |
| DEPP_WriteEnable | in | std_logic | Transfer direction control<br> `1` = read (Host from DEPP); `0` = write (Host to DEPP) |
| DEPP_Wait | out | std_logic | Handshake signal <br> `0` = ready for new cycle; `1` = closing current cycle and not ready for new cycle<br> Keep the signal low to delay the cycle length |
| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus; Tri-state |
#### FIFO-Data-Out
| Port name | Direction | Type | Description |
| ----------------------- | --------- | ---------------------------- | ----------------------------------------------------------------------- |
| DataOutFifo_Data | out | std_logic_vector(7 downto 0) | Data output corosponding to the address |
| DataOutFifo_Address | out | std_logic_vector(7 downto 0) | Address output |
| DataOutFifo_WriteEnable | out | std_logic | Valid data & adress output if `1`. Is only 1 cycle valid |
| DataOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `WriteEnable` signal |
#### FIFO-Data-In
| Port name | Direction | Type | Description |
| --------------------- | --------- | ---------------------------- | ------------------------------------------------------- |
| DataInFifo_Data | in | std_logic_vector(7 downto 0) | Data input |
| DataInFifo_EmptyFlag | in | std_logic | If the fifo is not empty, the module will read the data |
| DataInFifo_ReadEnable | out | std_logic | Is one cycle `1` to indicate that the data is read |
#### FIFO-Address-Out
| Port name | Direction | Type | Description |
| -------------------------- | --------- | ---------------------------- | ------------------------------------------------------------------------- |
| AddressOutFifo_Data | out | std_logic_vector(7 downto 0) | Address output for read requests |
| AddressOutFifo_WriteEnable | out | std_logic | Valid address output if `1`. Is only 1 cycle valid |
| AddressOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `RequestEnable` signal |
## Signals
| Name | Type | Description |
| ------------ | ----------------------------------------------------------------- | ----------- |
| RegistersIn | RegisterType | |
| RegistersOut | RegisterType | |
| EPPDInternal | std_logic_vector(7 downto 0) | |
| Adress | std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0) | |
| Intern_CE | std_logic | |
| Intern_RST | std_logic | |
| Name | Type | Description |
| ------------------------------ | ---------------------------- | --------------------------------------------------------------------------------------- |
| TempAddressRegister | std_logic_vector(7 downto 0) | Catch the address as long as the mode (read/write) has not yet been decided. |
| EPP_AddressEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal |
| EPP_DataEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal |
| Mode | ModeType | The current state of the main state machine |
| InterWriteEnableOut | std_logic | The output signals for the output data fifo |
| InterRequestEnable | std_logic | The output signals for the output address fifo |
| InterAddressEnable | std_logic | Intermediary signal to start the address write cycle |
| DataInFifo_DataAviable | std_logic | Negated `DataInFifo_EmptyFlag` signal |
## Types
| Name | Type | Description |
| ------------ | ---- | ----------- |
| RegisterType | | |
| Name | Type | Description |
| -------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------ |
| ModeType | (Idle,<br><span style="padding-left:20px"> RequestActive,<br><span style="padding-left:20px"> SetData,<br><span style="padding-left:20px"> WriteActive,<br><span style="padding-left:20px"> WaitForFallingDataEnable,<br><span style="padding-left:20px"> WaitingForFallingAddressEnable,<br><span style="padding-left:20px"> AdressActive) | The states of the main state machine |
## Functions
- min_bits_for_states <font id="function_arguments">(N : integer)</font> <font id="function_return">return integer</font>
- Function to calculate the number of bits needed to address the `N` registers
## Processes
- DEPP_AddrIn: ( DEPP_AddressEnable )
- DEPP_DIn: ( DEPP_DataEnable )
- DOutRegister: ( CLK )
- DInRegister: ( CLK )
- EPP_AddressEnableCatch: ( CLK )
- **Description**
Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` for the rising/falling edge detection.
- EPP_DataEnableCatch: ( CLK )
- **Description**
Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`. for the rising/falling edge detection.
- DataInFIFOMinimizeLatency: ( Mode, DataInFifo_DataAviable )
- **Description**
Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal if in the `RequestActive` mode: Minimize the latency of the data read.
- EPP_WaitManagement: ( CLK )
- EPP_AddressCatch: ( CLK )
- **Description**
Address write cycle: If the `DEPP_AddressEnable` signal rises, he `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `TempAddressRegister`.
- EPP_ReciveData: ( CLK )
- **Description**
Data write cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `DataOut`, the `TempAddressRegister` is stored in the `AddressOut` and the `WriteEnableOut` signal is set to `1`.
- EPP_ReciveRequest: ( CLK )
- **Description**
Data read cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is high (read) and the module is in idle state the `TempAddressRegister` is stored in the `RequestAddress` and the `RequestEnable` signal is set to `1`.
## State machines
![Diagram_state_machine_0](fsm_DEPP_00.svg "Diagram")

2
docs/DEPP/DEPP.svg
View File

File diff suppressed because one or more lines are too long
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 5.9 KiB

After

Width:  |  Height:  |  Size: 5.6 KiB

0
docs/Waveforms/EPP Address Write.json → docs/DEPP/Waveforms/EPP Address Write.json
View File

20
docs/DEPP/Waveforms/EPP Data Read.json Normal file
View File

@@ -0,0 +1,20 @@
{
"signal": [
{ "name": "DEPP_Bus", "wave": "zz...3...x", "data": ["Adress"] },
{ "node": "...J.K.L.M", "phase": 0.15 },
{ "name": "DEPP_WriteEnable", "wave": "x1........" },
{ "node": "...A...B", "phase": 0.15 },
{ "name": "DEPP_DataEnable", "wave": "1..0...1.." },
{ "node": "...E..FH.I", "phase": 0.15 },
{ "node": ".C.D.G", "phase": 0.15 },
{ "name": "DEPP_Wait", "wave": "x0....1..0" }
],
"head": {
"text": "EPP Data Read"
},
"foot": {
"text": "EPP Data Read Cycle Timing Diagram"
},
"edge": ["A+B min. 80 ns", "C+D min. 40 ns", "E+F 0 to 10 ms", "H+I 0 to 10 ms", "J+K max. 20 ns", "L+M min. 20 ns"
]
}

18
docs/DEPP/Waveforms/EPP Data Write.json Normal file
View File

@@ -0,0 +1,18 @@
{
"signal": [
{ "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Adress"] },
{ "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
{ "node": "...A...B", "phase": 0.15 },
{ "name": "DEPP_DataEnable", "wave": "1..0...1.." },
{ "node": "...E.F.H.I", "phase": 0.15 },
{ "node": ".C.D.G", "phase": 0.15 },
{ "name": "DEPP_Wait", "wave": "x0...1...0" }
],
"head": {
"text": "EPP Data Write"
},
"foot": {
"text": "EPP Data Write Cycle Timing Diagram"
},
"edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
}

145
docs/DEPP/fsm_DEPP_00.svg Normal file
View File

@@ -0,0 +1,145 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<!-- Generated by graphviz version 2.40.1 (20161225.0304)
-->
<!-- Title: state transitions Pages: 1 -->
<svg width="1127pt" height="352pt"
viewBox="0.00 0.00 1127.00 352.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 348)">
<title>state transitions</title>
<polygon fill="#ffffff" stroke="transparent" points="-4,4 -4,-348 1123,-348 1123,4 -4,4"/>
<g id="clust1" class="cluster state regular">
<title>cluster_Mode</title>
<path fill="none" stroke="#000000" stroke-width="2" d="M20,-8C20,-8 1099,-8 1099,-8 1105,-8 1111,-14 1111,-20 1111,-20 1111,-324 1111,-324 1111,-330 1105,-336 1099,-336 1099,-336 20,-336 20,-336 14,-336 8,-330 8,-324 8,-324 8,-20 8,-20 8,-14 14,-8 20,-8"/>
<text text-anchor="start" x="544.4964" y="-317.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">Mode</text>
</g>
<!-- Mode -->
<!-- Idle -->
<g id="node2" class="node state regular">
<title>Idle</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="920,-298 864,-298 864,-262 920,-262 920,-298"/>
<text text-anchor="start" x="882.3304" y="-276.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">Idle</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M876.3333,-263C876.3333,-263 907.6667,-263 907.6667,-263 913.3333,-263 919,-268.6667 919,-274.3333 919,-274.3333 919,-285.6667 919,-285.6667 919,-291.3333 913.3333,-297 907.6667,-297 907.6667,-297 876.3333,-297 876.3333,-297 870.6667,-297 865,-291.3333 865,-285.6667 865,-285.6667 865,-274.3333 865,-274.3333 865,-268.6667 870.6667,-263 876.3333,-263"/>
</g>
<!-- RequestActive -->
<g id="node5" class="node state regular">
<title>RequestActive</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="847.5,-216 748.5,-216 748.5,-180 847.5,-180 847.5,-216"/>
<text text-anchor="start" x="759.824" y="-194.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">RequestActive</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M760.8333,-181C760.8333,-181 835.1667,-181 835.1667,-181 840.8333,-181 846.5,-186.6667 846.5,-192.3333 846.5,-192.3333 846.5,-203.6667 846.5,-203.6667 846.5,-209.3333 840.8333,-215 835.1667,-215 835.1667,-215 760.8333,-215 760.8333,-215 755.1667,-215 749.5,-209.3333 749.5,-203.6667 749.5,-203.6667 749.5,-192.3333 749.5,-192.3333 749.5,-186.6667 755.1667,-181 760.8333,-181"/>
</g>
<!-- Idle&#45;&gt;RequestActive -->
<g id="edge1" class="edge transition">
<title>Idle&#45;&gt;RequestActive</title>
<path fill="none" stroke="#000000" d="M899.9839,-261.5765C902.7166,-252.2428 903.807,-241.1849 898,-233 892.5846,-225.367 875.6733,-218.272 857.2613,-212.4933"/>
<polygon fill="#000000" stroke="#000000" points="858.1324,-209.1008 847.5491,-209.5955 856.131,-215.8086 858.1324,-209.1008"/>
<text text-anchor="start" x="902" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterRequestEnable = &#39;1&#39; &#160;&#160;</text>
</g>
<!-- WaitForFallingDataEnable -->
<g id="node7" class="node state regular">
<title>WaitForFallingDataEnable</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="668,-52 506,-52 506,-16 668,-16 668,-52"/>
<text text-anchor="start" x="516.9944" y="-30.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WaitForFallingDataEnable</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M518.3333,-17C518.3333,-17 655.6667,-17 655.6667,-17 661.3333,-17 667,-22.6667 667,-28.3333 667,-28.3333 667,-39.6667 667,-39.6667 667,-45.3333 661.3333,-51 655.6667,-51 655.6667,-51 518.3333,-51 518.3333,-51 512.6667,-51 507,-45.3333 507,-39.6667 507,-39.6667 507,-28.3333 507,-28.3333 507,-22.6667 512.6667,-17 518.3333,-17"/>
</g>
<!-- Idle&#45;&gt;WaitForFallingDataEnable -->
<g id="edge2" class="edge transition">
<title>Idle&#45;&gt;WaitForFallingDataEnable</title>
<path fill="none" stroke="#000000" d="M920.292,-276.5913C955.4327,-271.7084 1012.3177,-261.4516 1025,-245 1028.2562,-240.7761 1028.2663,-237.2162 1025,-233 1016.2857,-221.7514 1007.6465,-229.03 994,-225 933.3441,-207.0874 919.9456,-196.9008 859,-180 825.5283,-170.718 812.2762,-181.2433 782.718,-163 772.7134,-156.8252 766,-154.2567 766,-142.5 766,-142.5 766,-142.5 766,-75 766,-54.8451 722.3359,-44.5978 678.1387,-39.3879"/>
<polygon fill="#000000" stroke="#000000" points="678.4421,-35.9003 668.1203,-38.2901 677.6795,-42.8586 678.4421,-35.9003"/>
<text text-anchor="start" x="782" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterWriteEnableOut = &#39;1&#39; &#160;&#160;</text>
</g>
<!-- WaitingForFallingAddressEnable -->
<g id="node8" class="node state regular">
<title>WaitingForFallingAddressEnable</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="279,-216 83,-216 83,-180 279,-180 279,-216"/>
<text text-anchor="start" x="93.6568" y="-194.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WaitingForFallingAddressEnable</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M95.3333,-181C95.3333,-181 266.6667,-181 266.6667,-181 272.3333,-181 278,-186.6667 278,-192.3333 278,-192.3333 278,-203.6667 278,-203.6667 278,-209.3333 272.3333,-215 266.6667,-215 266.6667,-215 95.3333,-215 95.3333,-215 89.6667,-215 84,-209.3333 84,-203.6667 84,-203.6667 84,-192.3333 84,-192.3333 84,-186.6667 89.6667,-181 95.3333,-181"/>
</g>
<!-- Idle&#45;&gt;WaitingForFallingAddressEnable -->
<g id="edge3" class="edge transition">
<title>Idle&#45;&gt;WaitingForFallingAddressEnable</title>
<path fill="none" stroke="#000000" d="M863.566,-279.8389C725.3287,-278.9185 129.0183,-273.3132 102.485,-245 93.9132,-235.8531 98.0847,-227.8797 107.9583,-221.2253"/>
<polygon fill="#000000" stroke="#000000" points="109.9548,-224.1186 116.9647,-216.1742 106.5307,-218.0132 109.9548,-224.1186"/>
<text text-anchor="start" x="102" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterAddressEnable = &#39;1&#39; &#160;&#160;</text>
</g>
<!-- AdressActive -->
<g id="node3" class="node state regular">
<title>AdressActive</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="108,-298 16,-298 16,-262 108,-262 108,-298"/>
<text text-anchor="start" x="26.9948" y="-276.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">AdressActive</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M28.3333,-263C28.3333,-263 95.6667,-263 95.6667,-263 101.3333,-263 107,-268.6667 107,-274.3333 107,-274.3333 107,-285.6667 107,-285.6667 107,-291.3333 101.3333,-297 95.6667,-297 95.6667,-297 28.3333,-297 28.3333,-297 22.6667,-297 17,-291.3333 17,-285.6667 17,-285.6667 17,-274.3333 17,-274.3333 17,-268.6667 22.6667,-263 28.3333,-263"/>
</g>
<!-- AdressActive&#45;&gt;WaitingForFallingAddressEnable -->
<g id="edge4" class="edge transition">
<title>AdressActive&#45;&gt;WaitingForFallingAddressEnable</title>
<path fill="none" stroke="#000000" d="M53.6738,-261.651C50.7763,-252.3377 49.5047,-241.2756 55.221,-233 58.7223,-227.9311 66.4079,-223.4367 76.343,-219.5015"/>
<polygon fill="#000000" stroke="#000000" points="77.7991,-222.6982 86.0438,-216.0442 75.4492,-216.1044 77.7991,-222.6982"/>
<text text-anchor="middle" x="56.3895" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
</g>
<!-- WriteActive -->
<g id="node4" class="node state regular">
<title>WriteActive</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="131,-134 49,-134 49,-98 131,-98 131,-134"/>
<text text-anchor="start" x="59.6694" y="-112.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WriteActive</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M61.3333,-99C61.3333,-99 118.6667,-99 118.6667,-99 124.3333,-99 130,-104.6667 130,-110.3333 130,-110.3333 130,-121.6667 130,-121.6667 130,-127.3333 124.3333,-133 118.6667,-133 118.6667,-133 61.3333,-133 61.3333,-133 55.6667,-133 50,-127.3333 50,-121.6667 50,-121.6667 50,-110.3333 50,-110.3333 50,-104.6667 55.6667,-99 61.3333,-99"/>
</g>
<!-- WriteActive&#45;&gt;WaitForFallingDataEnable -->
<g id="edge5" class="edge transition">
<title>WriteActive&#45;&gt;WaitForFallingDataEnable</title>
<path fill="none" stroke="#000000" d="M102.9925,-97.8732C113.4987,-84.8054 129.5431,-68.099 148,-60 178.8675,-46.4551 376.0667,-39.2249 495.4183,-36.0429"/>
<polygon fill="#000000" stroke="#000000" points="495.7448,-39.5356 505.6497,-35.7749 495.5614,-32.538 495.7448,-39.5356"/>
<text text-anchor="middle" x="133.3895" y="-72" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
</g>
<!-- SetData -->
<g id="node6" class="node state regular">
<title>SetData</title>
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="619.5,-134 554.5,-134 554.5,-98 619.5,-98 619.5,-134"/>
<text text-anchor="start" x="565.8262" y="-112.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">SetData</text>
<path fill="none" stroke="#000000" stroke-width="2" d="M566.8333,-99C566.8333,-99 607.1667,-99 607.1667,-99 612.8333,-99 618.5,-104.6667 618.5,-110.3333 618.5,-110.3333 618.5,-121.6667 618.5,-121.6667 618.5,-127.3333 612.8333,-133 607.1667,-133 607.1667,-133 566.8333,-133 566.8333,-133 561.1667,-133 555.5,-127.3333 555.5,-121.6667 555.5,-121.6667 555.5,-110.3333 555.5,-110.3333 555.5,-104.6667 561.1667,-99 566.8333,-99"/>
</g>
<!-- RequestActive&#45;&gt;SetData -->
<g id="edge6" class="edge transition">
<title>RequestActive&#45;&gt;SetData</title>
<path fill="none" stroke="#000000" d="M748.1387,-194.6548C697.9512,-190.3215 625.0074,-181.0743 603.71,-163 597.8995,-158.0689 594.1092,-150.9742 591.6368,-143.7861"/>
<polygon fill="#000000" stroke="#000000" points="595.0112,-142.8563 589.0163,-134.1206 588.2551,-144.688 595.0112,-142.8563"/>
<text text-anchor="start" x="603" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">DataInFifo_DataAviable = &#39;1&#39; &#160;&#160;</text>
</g>
<!-- SetData&#45;&gt;WaitForFallingDataEnable -->
<g id="edge7" class="edge transition">
<title>SetData&#45;&gt;WaitForFallingDataEnable</title>
<path fill="none" stroke="#000000" d="M587,-97.8015C587,-87.3976 587,-74.1215 587,-62.3768"/>
<polygon fill="#000000" stroke="#000000" points="590.5001,-62.1476 587,-52.1476 583.5001,-62.1476 590.5001,-62.1476"/>
<text text-anchor="middle" x="588.3895" y="-72" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
</g>
<!-- WaitForFallingDataEnable&#45;&gt;Idle -->
<g id="edge8" class="edge transition">
<title>WaitForFallingDataEnable&#45;&gt;Idle</title>
<path fill="none" stroke="#000000" d="M668.2862,-35.8361C769.716,-39.237 930,-48.762 930,-75 930,-142.5 930,-142.5 930,-142.5 930,-203.1048 1007.1476,-177.7252 1032,-233 1034.1871,-237.8643 1034.4752,-240.2758 1032,-245 1022.5408,-263.0535 968.5544,-272.2966 930.4611,-276.6359"/>
<polygon fill="#000000" stroke="#000000" points="929.7602,-273.1908 920.1884,-277.733 930.5036,-280.1512 929.7602,-273.1908"/>
<text text-anchor="start" x="933" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">EPP_DataEnableShiftRegister = &quot;01&quot; &#160;&#160;</text>
</g>
<!-- WaitForFallingDataEnable&#45;&gt;Idle -->
<g id="edge9" class="edge transition">
<title>WaitForFallingDataEnable&#45;&gt;Idle</title>
<path fill="none" stroke="#000000" d="M505.8101,-37.6698C380.4322,-43.8843 154,-57.5265 154,-75 154,-142.5 154,-142.5 154,-142.5 154,-164.9879 178.5232,-157.2326 200.259,-163 204.8924,-164.2294 883.6029,-229.6178 887,-233 891.8084,-237.7872 894.0322,-244.3853 894.8394,-251.1251"/>
<polygon fill="#000000" stroke="#000000" points="891.3527,-251.6864 895.1098,-261.5927 898.3503,-251.5056 891.3527,-251.6864"/>
<text text-anchor="start" x="200" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">(EPP_DataEnableShiftRegister = &quot;11&quot;) and (EPP_AddressEnableShiftRegister = &quot;11&quot;) &#160;&#160;</text>
</g>
<!-- WaitingForFallingAddressEnable&#45;&gt;Idle -->
<g id="edge10" class="edge transition">
<title>WaitingForFallingAddressEnable&#45;&gt;Idle</title>
<path fill="none" stroke="#000000" d="M205.9437,-216.0653C221.858,-226.5398 243.3882,-238.8433 264.457,-245 320.8058,-261.4663 725.8724,-274.9814 853.5555,-278.8711"/>
<polygon fill="#000000" stroke="#000000" points="853.5512,-282.3725 863.6524,-279.1762 853.7627,-275.3757 853.5512,-282.3725"/>
<text text-anchor="start" x="264" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">EPP_AddressEnableShiftRegister = &quot;01&quot; &#160;&#160;</text>
</g>
<!-- WaitingForFallingAddressEnable&#45;&gt;Idle -->
<g id="edge11" class="edge transition">
<title>WaitingForFallingAddressEnable&#45;&gt;Idle</title>
<path fill="none" stroke="#000000" d="M279.161,-207.1491C331.3792,-212.879 396.5036,-221.4016 454,-233 473.5583,-236.9454 477.6274,-241.4375 497.259,-245 626.3595,-268.4277 782.1784,-276.3738 853.261,-278.9031"/>
<polygon fill="#000000" stroke="#000000" points="853.4101,-282.41 863.523,-279.2511 853.6474,-275.4141 853.4101,-282.41"/>
<text text-anchor="start" x="497" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">(EPP_DataEnableShiftRegister = &quot;11&quot;) and (EPP_AddressEnableShiftRegister = &quot;11&quot;) &#160;&#160;</text>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 13 KiB

1
docs/DEPP/wavedrom_91sO2.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 48 KiB

0
docs/DEPP/wavedrom_SDc50.svg → docs/DEPP/wavedrom_HWwR0.svg
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 47 KiB

After

Width:  |  Height:  |  Size: 47 KiB

1
docs/DEPP/wavedrom_ypdi1.svg Normal file
View File

File diff suppressed because one or more lines are too long
Side by Side

After

Width:  |  Height:  |  Size: 47 KiB

BIN
docs/Logic Analyzer Captures/Address Write Cycle.webp Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 224 KiB

BIN
docs/Logic Analyzer Captures/Data Read Cycle.webp Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 201 KiB

BIN
docs/Logic Analyzer Captures/Data Write Cycle.webp Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 202 KiB