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* Enhanced edge detection in DEPP

Updated the DEPP VHDL component with clearer comment annotations and modified edge detection logic for address and data enable signals. Additionally, refined the main state machine by explicitly adding states for edge waiting periods and defining behaviors for each state, specifically regarding the handling of output FIFO signals and cycle initiation. Updated the edge detection mechanism within the address and data processing workflows, improving cycle handling for idle, address, and data states to better signal the transitions and manage the bus as well as the request and write enable signals.

* Implement FIFO compatible interface and update waveforms

Enhanced DEPP documentation and diagrams to reflect a transition to FIFO compatible interfaces for data traffic efficiency. Updated waveforms depict the revised cycle timings for data/address commands and address acknowledgment, ensuring clarity on the implemented protocol changes.

* Refine DEPP VHDL port naming for clarity

Updated the DEPP VHDL entity's port naming convention to enhance readability and consistency across data and address lines. Introduced clear "Fifo" and "AddressOut" prefixes as per FIFO compatible interfaces, replacing generic data and address signal names. This renaming also strengthens the association between ports and their respective data flow. Additional changes include:
- Replaced 'DataAviable' with a negated 'DataInFifo_EmptyFlag' for immediate data availability check.
- Streamlined write enable signals alignment with the new naming convention.
- Redesigned read-enable logic to minimize latency in 'RequestActive' mode by directly relaying the 'DataInFifo_DataAviable' status.
- Simplified and restructured bus wait management states to reflect the updated port names and signal handling improvements.
- Removed obsolete comments and updated documentation to accurately reflect the current interface functionality and structure.

* Enhanced DEPP module docs and waveform references

- Updated the DEPP module documentation to improve clarity and readability.
- Refactoring included renaming of waveform files for consistency and eliminating unnecessary whitespace.
- Revised virtual bus interface descriptions for better accuracy and cleared up the ambiguity in port names and their corresponding descriptions.
- Streamlined the ports and signals tables to enhance document structure and coherence.
- Modified the state machine SVG file for an up-to-date representation of the module design.
- Integrated additional waveform diagrams to detail the EPP (Enhanced Parallel Port) bus cycles within the documentation.

* Optimized EPP state machine timing

Refactored the EPP (Enhanced Parallel Port) VHDL state machine to streamline the signal handling for different operating states. This optimization includes removing redundant assignments to the `DEPP_Wait` signal in intermediary states and ensuring it is only held high for a minimum of one cycle where necessary. These modifications enhance the clarity of state transitions and may improve the system's timing performance, particularly for the start of read, write, and address cycles.

Additionally, the documentation is updated to include measured data rates, aiding in setting performance expectations.

* Enhanced UCF readability and added LA constraints

Reformatted the pin constraints section in Nexys2Test.ucf to improve readability, adding descriptive comments for RST, DataOutFullFlag, and RequestFullFlag signals. Removed unnecessary net constraints related to DEPP interface signals. Extended the UCF to include configuration for the Logic Analyzer (LA), specifying appropriate locations and providing comments linking net names to their corresponding physical connectors.

* Refactor signal handling and add Logic Analyzer output

Updated the Nexys2Test VHDL entity to streamline signal handling and add support for a Logic Analyzer interface. Removed commented-out attributes for virtual bus and related signals, which simplifies the interface section. Introduced new outputs for the Logic Analyzer to monitor various signals such as address, data enable, write enable, and wait signals, which improves debug and testing capabilities. In the architecture, redundant process handling DEPP_Wait has been removed to reduce complexity, and DEPP_Bus is now directly assigned. Updated the main process to simplify LED assignments and fixed an incorrect value for DataInFifo_EmptyFlag, enhancing signal accuracy and conforming to expected logic levels. These changes contribute to a more maintainable and understandable codebase.

* Update EPP documentation with data rate and refreshed diagrams

- Added the measured data transfer rate to the DEPP documentation.
- Replaced EPP bus waveform diagrams with updated versions.
- Resized and restructured the DEPP FSM SVG for better legibility, including adjustments to cluster dimensions, node positions, edges, and transitions.
- Renamed waveform SVG files for a consistent naming convention.

* Added logic analyzer capture visuals for documentation

* Added MIT License and enhanced README for DEPP module

Implemented an MIT License file and updated the README to provide comprehensive documentation for the VHDL Module designed for the Digilent Asynchronous Parallel Port Interface. The README now includes an overview of the module's purpose, features such as the measured data rate, visual diagrams for bus cycles, a detailed port definition table, module dependencies, contribution guidelines, licensing information, and acknowledgments, improving clarity and usability for end-users and contributors.
Co-authored-by: Max P <Mail@MPassarello.de>
Co-committed-by: Max P <Mail@MPassarello.de>
This commit is contained in:
0xMax42
2024-03-08 23:52:17 +01:00
committed by maxp
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# English
# VHDL Module for the Digilent Asynchronous Parallel Port Interface (DEPP)
## VHDL Project Template Using Xilinx Build Tools with Makefile
## Overview
Welcome to the VHDL Project Template repository. This project is designed to streamline your FPGA development process using the Xilinx ISE Build Tools, integrated with a convenient Makefile approach for building and synthesizing your VHDL designs.
The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface for use with Digilent FPGA boards. It facilitates communication between a host computer and the FPGA via the Digilent Adept software, supporting operations such as address write, data write, and data read cycles.
### Using the Makefile
## Features
To use the Makefile for building your VHDL projects, ensure you have the Xilinx Build Tools installed on your system. The Makefile is specifically configured to work with these tools to automate the build process.
- Designed for integration with Digilent FPGA boards.
- Supports data transfers with Digilent Adept software.
- Measured data rate of approximately 4.68 kByte/s.
For detailed instructions on how to use the Makefile, please refer to the following URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). This page contains comprehensive guidance on setup and usage to get you started quickly.
## Bus Cycles Visualized
### Directory Structure
- EPP Address Write Cycle
![Waveform of the EPP Address Write Cycle](docs/DEPP/wavedrom_HWwR0.svg "EPP Address Write")
The project is organized into various subdirectories, each serving a specific role in the development process. For an explanation of the directory structure and the contents of each subdirectory, please refer to the `README.md` files located within the subdirectories. These documents provide valuable insights into how the project is organized and how to navigate the files and folders efficiently.
- EPP Data Write Cycle
![Waveform of the EPP Data Write Cycle](docs/DEPP/wavedrom_ypdi1.svg "EPP Data Write")
### Getting Started
- EPP Data Read Cycle
![Waveform of the EPP Data Read Cycle](docs/DEPP/wavedrom_91sO2.svg "EPP Data Read")
To begin using this VHDL Project Template, clone the repository to your local machine and follow the instructions provided in the subdirectory `README.md` files to understand the project layout. Then, head over to the URL mentioned above for details on using the Makefile with the Xilinx Build Tools.
## Port Definitions
Thank you for choosing this VHDL Project Template. We hope it accelerates your development process and helps you achieve your project goals efficiently.
| Port Name | Direction | Type | Description |
| ---------------- | --------- | ----------- | -------------------------------------------------- |
| CLK | in | std_logic | Clock signal. Rising edge triggered. |
| CE | in | std_logic | Chip enable. `1` = enabled, `0` = disabled. |
| RST | in | std_logic | Reset signal. `1` = reset, `0` = normal operation. |
| EPP-Interface | out | Virtual bus | EPP Interface for address and data operations. |
| FIFO-Data-Out | out | Virtual bus | FIFO compatible data and address output interface. |
| FIFO-Data-In | in | Virtual bus | FIFO compatible data input interface. |
| FIFO-Address-Out | out | Virtual bus | FIFO compatible request address output interface. |
---
Detailed information on virtual bus port configurations can be found within the [module's documentation](docs/DEPP/DEPP.md).
# Deutsch
## Dependencies
## VHDL-Projektvorlage unter Verwendung von Xilinx Build Tools mit Makefile
The module depends on standard logic and numeric libraries available in VHDL. Ensure you have the latest version of the Digilent Adept software for proper interfacing with the module.
Willkommen im Repository der VHDL-Projektvorlage. Dieses Projekt wurde entwickelt, um Ihren FPGA-Entwicklungsprozess mit den Xilinx ISE Build Tools zu vereinfachen, integriert mit einem praktischen Makefile-Ansatz zum Bauen und Synthetisieren Ihrer VHDL-Designs.
## Contributing
### Verwendung des Makefiles
Contributions to improve the module or extend its capabilities are welcome. Please adhere to the existing coding standards and provide documentation for any changes made.
Um das Makefile für den Bau Ihrer VHDL-Projekte zu verwenden, stellen Sie sicher, dass die Xilinx Build Tools auf Ihrem System installiert sind. Das Makefile ist speziell so konfiguriert, dass es mit diesen Tools arbeitet, um den Bauprozess zu automatisieren.
## License
Für detaillierte Anweisungen zur Verwendung des Makefiles besuchen Sie bitte die folgende URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). Diese Seite enthält umfassende Anleitungen zur Einrichtung und Verwendung, damit Sie schnell starten können.
This module is open source and is distributed under the MIT license. Please see the [LICENSE](LICENSE) file for full details.
### Verzeichnisstruktur
## Acknowledgments
Das Projekt ist in verschiedene Unterverzeichnisse organisiert, von denen jedes eine spezifische Rolle im Entwicklungsprozess spielt. Für eine Erklärung der Verzeichnisstruktur und des Inhalts jedes Unterverzeichnisses beachten Sie bitte die `README.md`-Dateien, die sich in den Unterverzeichnissen befinden. Diese Dokumente bieten wertvolle Einblicke, wie das Projekt organisiert ist und wie Sie effizient durch die Dateien und Ordner navigieren.
### Erste Schritte
Um mit dieser VHDL-Projektvorlage zu beginnen, klonen Sie das Repository auf Ihre lokale Maschine und folgen Sie den Anweisungen in den `README.md`-Dateien der Unterverzeichnisse, um das Layout des Projekts zu verstehen. Anschließend besuchen Sie die oben genannte URL für Details zur Verwendung des Makefiles mit den Xilinx Build Tools.
Vielen Dank, dass Sie sich für diese VHDL-Projektvorlage entschieden haben. Wir hoffen, dass sie Ihren Entwicklungsprozess beschleunigt und Ihnen hilft, Ihre Projektziele effizient zu erreichen.
Special thanks to the Digilent team for providing a reference manual in which the diagrams and the description in the text are contradictory ;-)