From 526ffaa790e50a2ccab47ac6b3342163644f4e80 Mon Sep 17 00:00:00 2001 From: MaxP Date: Wed, 16 Apr 2025 17:30:50 +0000 Subject: [PATCH] Misc --- libs/Pipeline-AXI-Handshake | 2 +- project.cfg | 117 ++++++++++++++++++++++++++++++++++++ tests/AsyncFIFO_tb.wcfg | 100 ++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 project.cfg create mode 100644 tests/AsyncFIFO_tb.wcfg diff --git a/libs/Pipeline-AXI-Handshake b/libs/Pipeline-AXI-Handshake index 59e8302..31ce816 160000 --- a/libs/Pipeline-AXI-Handshake +++ b/libs/Pipeline-AXI-Handshake @@ -1 +1 @@ -Subproject commit 59e8302a48eb3bbfcf579b98a714581880a7786d +Subproject commit 31ce81681696907dcaa3e1b48ac6f855f55ea4b4 diff --git a/project.cfg b/project.cfg new file mode 100644 index 0000000..345ee80 --- /dev/null +++ b/project.cfg @@ -0,0 +1,117 @@ +## Main settings.. ## + +# Project name +# @remark The name of the project is used as default name for the top module and the ucf file +PROJECT = AsyncFIFO + +# Target device +# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136 +TARGET_PART = xc3s1200e-4-fg320 + +# Path to the Xilinx ISE installation +XILINX = /opt/Xilinx/14.7/ISE_DS/ISE + +# Optional the name of the top module (default is the project name) +TOPLEVEL = AsyncFIFO + +# Optional the path/name of the ucf file (default is the project name) +CONSTRAINTS = src/AsyncFIFO.ucf + +# Optional a target to copy the bit file to (make copy) +# COPY_TARGET_DIR = + +## ## ## ## ## ## ## ## +# --------------------- + +## Source files settings.. ## +# The source files to be compiled +# @example `VSOURCE += src/main.v` (add a single Verilog file per line) +# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line) + +# VHDSOURCE += src/VGATimingGenerator_pb.vhd +# VHDSOURCE += src/VGATimingGenerator_test.vhd +VHDSOURCE += libs/GrayCounter.vhd +VHDSOURCE += src/AsyncFIFO.vhd +VHDSOURCE += libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd + +## Test files settings.. ## +# The testbench files to be compiled +# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line) +# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line) + +#VHDTEST += tests/VGATimingGenerator_tb.vhd +VHDTEST += tests/AsyncFIFO_tb.vhd + +## ## ## ## ## ## ## ## +# --------------------- + +## ISE executable settings.. ## + +# General command line options to be passed to all ISE executables (default is `-intstyle xflow`) +# COMMON_OPTS = + +# Options for the XST synthesizer +# @example -register_balancing (yes|no) +# @example -opt_mode (speed|area) +# @example -opt_level (1|2) +XST_OPTS = + +# Options for the NGDBuild tool +# NGDBUILD_OPTS = + +# Options for the MAP tool +# @example -mt 2 (multi-threading with 2 threads) +# @example -cm speed (speed optimization) +# @example -ol high +# @example -detail +# @example -timing +MAP_OPTS = -detail + +# Options for the PAR tool +# @example -mt 2 (multi-threading with 2 threads) +# @example -ol high +PAR_OPTS = + +# Options for the BitGen tool +# @example -g Compress (compress bitstream) +# @example -g StartupClk:Cclk (specify the startup clock to onboard clock) +# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock) +BITGEN_OPTS = -g StartupClk:JtagClk + +# Options for the Trace tool +# TRACE_OPTS = + +# Options for the Fuse tool +# FUSE_OPTS = + +# Options for the ISim simulator +# @example -gui (start the simulator in GUI mode) +# ISIM_OPTS = + +# Options for the ISim batch file +# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit +# ISIM_CMD = vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit + +## ## ## ## ## ## ## ## +# --------------------- + +## Programmer settings.. ## + +# The programmer to use +# @example impact | digilent | xc3sprog +# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory.. +PROGRAMMER = + +## Digilent JTAG cable settings + +# @remark Use the `djtgcfg enum` command to list all available devices +# DJTG_DEVICE = DOnbUsb + +# The index of the JTAG device for the `prog` target +# DJTG_INDEX = 0 + +# The index of the flash device for the `flash` target +# DJTG_FLASH_INDEX = 1 + +## ## ## ## ## ## ## ## +# --------------------- \ No newline at end of file diff --git a/tests/AsyncFIFO_tb.wcfg b/tests/AsyncFIFO_tb.wcfg new file mode 100644 index 0000000..cf18ba2 --- /dev/null +++ b/tests/AsyncFIFO_tb.wcfg @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + Write + label + 128 128 255 + 230 230 230 + + + i_write_clk + i_write_clk + true + #ff0000 + + + i_write_ce + i_write_ce + + + i_write_data[31:0] + i_write_data[31:0] + HEXRADIX + + + r_write_pointer[3:0] + r_write_pointer[3:0] + HEXRADIX + + + r_read_pointersync[3:0] + r_read_pointersync[3:0] + HEXRADIX + + + r_write_pointerlookahead[3:0] + r_write_pointerlookahead[3:0] + HEXRADIX + + + o_write_ready + o_write_ready + + + i_write_valid + i_write_valid + + + Read + label + 128 128 255 + 230 230 230 + + + i_read_clk + i_read_clk + true + #ff0000 + + + i_read_ce + i_read_ce + + + o_read_data[31:0] + o_read_data[31:0] + HEXRADIX + + + r_read_pointer[3:0] + r_read_pointer[3:0] + HEXRADIX + + + r_write_pointersync[3:0] + r_write_pointersync[3:0] + HEXRADIX + + + o_read_valid + o_read_valid + + + i_read_ready + i_read_ready + +