library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity AXI_Handshaking_Scheduler_4 is
    generic (
        G_DataWidth : integer := 8;
        G_InBufferStages : integer := 1;
        G_OutBufferStages : integer := 1
    );
    port (
        --@ Clock signal; (**Rising edge** triggered)
        I_CLK : in std_logic;
        --@ Clock enable signal (**Active high**)
        I_CE : in std_logic;
        --@ Synchronous reset signal (**Active high**)
        I_RST : in std_logic;

        --@ @virtualbus P0 @dir in P0 interface
        I_P0_Valid : in std_logic := '0';
        O_P0_Ready : out std_logic := '0';
        I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        --@ @end
        --@ @virtualbus P1 @dir in P1 interface
        I_P1_Valid : in std_logic := '0';
        O_P1_Ready : out std_logic := '0';
        I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        --@ @end
        --@ @virtualbus P2 @dir in P2 interface
        I_P2_Valid : in std_logic := '0';
        O_P2_Ready : out std_logic := '0';
        I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        --@ @end
        --@ @virtualbus P3 @dir in P3 interface
        I_P3_Valid : in std_logic := '0';
        O_P3_Ready : out std_logic := '0';
        I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        --@ @end

        --@ @virtualbus Out @dir out Output interface
        O_Out_Valid : out std_logic := '0';
        I_Out_Ready : in std_logic := '0';
        O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        O_Out_Address : out std_logic_vector(1 downto 0) := (others => '0')
        --@ @end
    );
end entity AXI_Handshaking_Scheduler_4;

architecture Rtl of AXI_Handshaking_Scheduler_4 is
    signal R_SelectRotator : unsigned(1 downto 0) := (others => '0');
    signal R1_SelectRotator : unsigned(1 downto 0) := (others => '0');

    signal C_Select : std_logic_vector(3 downto 0) := (others => '0');
    signal C_Code : std_logic_vector(1 downto 0) := (others => '0');
    signal R_Code : std_logic_vector(1 downto 0) := (others => '0');
    signal C_CodeUnrotated : std_logic_vector(1 downto 0) := (others => '0');

    signal S_P0_InBufferEnable : std_logic := '0';
    signal S_P0_Ready : std_logic := '0';
    signal S_P0_Valid : std_logic := '0';
    signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P1_InBufferEnable : std_logic := '0';
    signal S_P1_Ready : std_logic := '0';
    signal S_P1_Valid : std_logic := '0';
    signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P2_InBufferEnable : std_logic := '0';
    signal S_P2_Ready : std_logic := '0';
    signal S_P2_Valid : std_logic := '0';
    signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P3_InBufferEnable : std_logic := '0';
    signal S_P3_Ready : std_logic := '0';
    signal S_P3_Valid : std_logic := '0';
    signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');

    signal S_OutBufferEnable : std_logic := '0';
    signal S_Out_Ready : std_logic := '0';
    signal S_Out_Valid : std_logic := '0';
    signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_Out_Address : std_logic_vector(1 downto 0) := (others => '0');
begin

    I_P0_InBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_InBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P0_InBufferEnable,
            I_Valid => I_P0_Valid,
            O_Ready => O_P0_Ready,
            O_Valid => S_P0_Valid,
            I_Ready => S_P0_Ready
        );

    I_P0_InBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P0_InBufferEnable,
            I_Data => I_P0_Data,
            O_Data => S_P0_Data
        );
    I_P1_InBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_InBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P1_InBufferEnable,
            I_Valid => I_P1_Valid,
            O_Ready => O_P1_Ready,
            O_Valid => S_P1_Valid,
            I_Ready => S_P1_Ready
        );

    I_P1_InBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P1_InBufferEnable,
            I_Data => I_P1_Data,
            O_Data => S_P1_Data
        );
    I_P2_InBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_InBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P2_InBufferEnable,
            I_Valid => I_P2_Valid,
            O_Ready => O_P2_Ready,
            O_Valid => S_P2_Valid,
            I_Ready => S_P2_Ready
        );

    I_P2_InBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P2_InBufferEnable,
            I_Data => I_P2_Data,
            O_Data => S_P2_Data
        );
    I_P3_InBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_InBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P3_InBufferEnable,
            I_Valid => I_P3_Valid,
            O_Ready => O_P3_Ready,
            O_Valid => S_P3_Valid,
            I_Ready => S_P3_Ready
        );

    I_P3_InBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P3_InBufferEnable,
            I_Data => I_P3_Data,
            O_Data => S_P3_Data
        );

    I_PriorityEncoder_4 : entity work.PriorityEncoder_4
        port map(
            I_Select => C_Select,
            O_Code => C_Code
        );

    P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid)
    begin
        case R_SelectRotator is when "00" =>
                C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
            when "01" =>
                C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P0_Valid;
            when "10" =>
                C_Select <= S_P2_Valid & S_P3_Valid & S_P0_Valid & S_P1_Valid;
            when "11" =>
                C_Select <= S_P3_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
            when others =>
                C_Select <= (others => '-');
        end case;
    end process;

    P_CodeUnrotating : process (R_Code, R1_SelectRotator)
    begin
        C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
    end process;

    P_OutMux : process (
        C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_Out_Ready)
    begin
        S_Out_Valid <= '0';
        S_P0_Ready <= '0';
        S_P1_Ready <= '0';
        S_P2_Ready <= '0';
        S_P3_Ready <= '0';
        S_Out_Data <= (others => '-');
        S_Out_Address <= C_CodeUnrotated;

        case C_CodeUnrotated is when "00" =>
                S_Out_Valid <= S_P0_Valid;
                S_P0_Ready <= S_Out_Ready;
                S_Out_Data <= S_P0_Data;
            when "01" =>
                S_Out_Valid <= S_P1_Valid;
                S_P1_Ready <= S_Out_Ready;
                S_Out_Data <= S_P1_Data;
            when "10" =>
                S_Out_Valid <= S_P2_Valid;
                S_P2_Ready <= S_Out_Ready;
                S_Out_Data <= S_P2_Data;
            when "11" =>
                S_Out_Valid <= S_P3_Valid;
                S_P3_Ready <= S_Out_Ready;
                S_Out_Data <= S_P3_Data;
            when others =>
                S_Out_Address <= (others => '-');
        end case;
    end process;

    P_SelectRotator : process (I_CLK)
    begin
        if rising_edge(I_CLK) then
            if I_CE = '1' then
                if I_RST = '1' then
                    R_SelectRotator <= (others => '0');
                    R1_SelectRotator <= (others => '0');
                    R_Code <= (others => '0');
                else
                    R1_SelectRotator <= R_SelectRotator;
                    R_Code <= C_Code;
                    if I_Out_Ready = '1' then
                        R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
                    end if;
                end if;
            end if;
        end if;
    end process P_SelectRotator;

    I_OutBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_OutBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_OutBufferEnable,
            I_Valid => S_Out_Valid,
            O_Ready => S_Out_Ready,
            O_Valid => O_Out_Valid,
            I_Ready => I_Out_Ready
        );

    I_OutDataBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_OutBufferEnable,
            I_Data => S_Out_Data,
            O_Data => O_Out_Data
        );

    I_OutAddressBuffer : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => 2,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_OutBufferEnable,
            I_Data => S_Out_Address,
            O_Data => O_Out_Address
        );
end architecture;