430 lines
14 KiB
VHDL
430 lines
14 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity AXI_HS_MUX_8 is
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generic (
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G_DataWidth : integer := 8;
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G_AddressWidth : integer := 3;
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G_InBufferStages : integer := 1;
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G_OutBufferStages : integer := 1
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);
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port (
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--@ Clock signal; (**Rising edge** triggered)
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I_CLK : in std_logic;
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--@ Clock enable signal (**Active high**)
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I_CE : in std_logic;
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--@ Synchronous reset signal (**Active high**)
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I_RST : in std_logic;
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--@ @virtualbus Input @dir in Input Interface
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I_PIn_Valid : in std_logic := '0';
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O_PIn_Ready : out std_logic := '0';
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I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P0 @dir out P0 interface
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O_P0_Valid : out std_logic := '0';
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I_P0_Ready : in std_logic := '0';
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O_P0_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P1 @dir out P1 interface
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O_P1_Valid : out std_logic := '0';
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I_P1_Ready : in std_logic := '0';
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O_P1_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P2 @dir out P2 interface
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O_P2_Valid : out std_logic := '0';
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I_P2_Ready : in std_logic := '0';
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O_P2_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P3 @dir out P3 interface
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O_P3_Valid : out std_logic := '0';
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I_P3_Ready : in std_logic := '0';
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O_P3_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P4 @dir out P4 interface
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O_P4_Valid : out std_logic := '0';
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I_P4_Ready : in std_logic := '0';
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O_P4_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P5 @dir out P5 interface
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O_P5_Valid : out std_logic := '0';
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I_P5_Ready : in std_logic := '0';
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O_P5_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P6 @dir out P6 interface
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O_P6_Valid : out std_logic := '0';
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I_P6_Ready : in std_logic := '0';
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O_P6_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
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--@ @virtualbus P7 @dir out P7 interface
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O_P7_Valid : out std_logic := '0';
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I_P7_Ready : in std_logic := '0';
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O_P7_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0') --@ @end
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);
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end entity AXI_HS_MUX_8;
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architecture Rtl of AXI_HS_MUX_8 is
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signal S_PIn_BufferEnable : std_logic := '0';
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signal S_PIn_Valid : std_logic := '0';
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signal S_PIn_Ready : std_logic := '0';
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signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
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signal S_P0_BufferEnable : std_logic := '0';
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signal S_P0_Valid : std_logic := '0';
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signal S_P0_Ready : std_logic := '0';
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signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P1_BufferEnable : std_logic := '0';
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signal S_P1_Valid : std_logic := '0';
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signal S_P1_Ready : std_logic := '0';
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signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P2_BufferEnable : std_logic := '0';
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signal S_P2_Valid : std_logic := '0';
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signal S_P2_Ready : std_logic := '0';
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signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P3_BufferEnable : std_logic := '0';
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signal S_P3_Valid : std_logic := '0';
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signal S_P3_Ready : std_logic := '0';
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signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P4_BufferEnable : std_logic := '0';
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signal S_P4_Valid : std_logic := '0';
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signal S_P4_Ready : std_logic := '0';
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signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P5_BufferEnable : std_logic := '0';
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signal S_P5_Valid : std_logic := '0';
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signal S_P5_Ready : std_logic := '0';
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signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P6_BufferEnable : std_logic := '0';
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signal S_P6_Valid : std_logic := '0';
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signal S_P6_Ready : std_logic := '0';
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signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P7_BufferEnable : std_logic := '0';
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signal S_P7_Valid : std_logic := '0';
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signal S_P7_Ready : std_logic := '0';
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signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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begin
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I_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_PIn_BufferEnable,
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I_Valid => I_PIn_Valid,
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O_Ready => O_PIn_Ready,
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O_Valid => S_PIn_Valid,
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I_Ready => S_PIn_Ready
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);
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I_InBufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PIn_BufferEnable,
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I_Data => I_PIn_Data,
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O_Data => R_PIn_Data
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);
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I_InBufferAddress : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_AddressWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PIn_BufferEnable,
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I_Data => I_PIn_Address,
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O_Data => R_PIn_Address
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);
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P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data, S_P0_Ready, S_P1_Ready, S_P2_Ready, S_P3_Ready, S_P4_Ready, S_P5_Ready, S_P6_Ready, S_P7_Ready)
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begin
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S_PIn_Ready <= '0';
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S_P0_Valid <= '0';
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S_P0_Data <= (others => '-');
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S_P1_Valid <= '0';
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S_P1_Data <= (others => '-');
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S_P2_Valid <= '0';
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S_P2_Data <= (others => '-');
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S_P3_Valid <= '0';
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S_P3_Data <= (others => '-');
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S_P4_Valid <= '0';
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S_P4_Data <= (others => '-');
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S_P5_Valid <= '0';
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S_P5_Data <= (others => '-');
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S_P6_Valid <= '0';
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S_P6_Data <= (others => '-');
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S_P7_Valid <= '0';
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S_P7_Data <= (others => '-');
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case to_integer(unsigned(R_PIn_Address)) is
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when 0 =>
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S_P0_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P0_Ready;
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S_P0_Data <= R_PIn_Data;
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when 1 =>
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S_P1_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P1_Ready;
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S_P1_Data <= R_PIn_Data;
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when 2 =>
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S_P2_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P2_Ready;
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S_P2_Data <= R_PIn_Data;
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when 3 =>
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S_P3_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P3_Ready;
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S_P3_Data <= R_PIn_Data;
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when 4 =>
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S_P4_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P4_Ready;
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S_P4_Data <= R_PIn_Data;
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when 5 =>
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S_P5_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P5_Ready;
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S_P5_Data <= R_PIn_Data;
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when 6 =>
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S_P6_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P6_Ready;
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S_P6_Data <= R_PIn_Data;
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when 7 =>
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S_P7_Valid <= S_PIn_Valid;
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S_PIn_Ready <= S_P7_Ready;
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S_P7_Data <= R_PIn_Data;
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when others =>
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null;
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end case;
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end process P_MUX;
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I_P0_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P0_BufferEnable,
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I_Valid => S_P0_Valid,
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O_Ready => S_P0_Ready,
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O_Valid => O_P0_Valid,
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I_Ready => I_P0_Ready
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);
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I_P0_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P0_BufferEnable,
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I_Data => S_P0_Data,
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O_Data => O_P0_Data
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);
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I_P1_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P1_BufferEnable,
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I_Valid => S_P1_Valid,
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O_Ready => S_P1_Ready,
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O_Valid => O_P1_Valid,
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I_Ready => I_P1_Ready
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);
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I_P1_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P1_BufferEnable,
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I_Data => S_P1_Data,
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O_Data => O_P1_Data
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);
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I_P2_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P2_BufferEnable,
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I_Valid => S_P2_Valid,
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O_Ready => S_P2_Ready,
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O_Valid => O_P2_Valid,
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I_Ready => I_P2_Ready
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);
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I_P2_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P2_BufferEnable,
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I_Data => S_P2_Data,
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O_Data => O_P2_Data
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);
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I_P3_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P3_BufferEnable,
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I_Valid => S_P3_Valid,
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O_Ready => S_P3_Ready,
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O_Valid => O_P3_Valid,
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I_Ready => I_P3_Ready
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);
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I_P3_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P3_BufferEnable,
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I_Data => S_P3_Data,
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O_Data => O_P3_Data
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);
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I_P4_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P4_BufferEnable,
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I_Valid => S_P4_Valid,
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O_Ready => S_P4_Ready,
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O_Valid => O_P4_Valid,
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I_Ready => I_P4_Ready
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);
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I_P4_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P4_BufferEnable,
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I_Data => S_P4_Data,
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O_Data => O_P4_Data
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);
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I_P5_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P5_BufferEnable,
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I_Valid => S_P5_Valid,
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O_Ready => S_P5_Ready,
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O_Valid => O_P5_Valid,
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I_Ready => I_P5_Ready
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);
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I_P5_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P5_BufferEnable,
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I_Data => S_P5_Data,
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O_Data => O_P5_Data
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);
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I_P6_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P6_BufferEnable,
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I_Valid => S_P6_Valid,
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O_Ready => S_P6_Ready,
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O_Valid => O_P6_Valid,
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I_Ready => I_P6_Ready
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);
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I_P6_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P6_BufferEnable,
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I_Data => S_P6_Data,
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O_Data => O_P6_Data
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);
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I_P7_BufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P7_BufferEnable,
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I_Valid => S_P7_Valid,
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O_Ready => S_P7_Ready,
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O_Valid => O_P7_Valid,
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I_Ready => I_P7_Ready
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);
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I_P7_BufferData : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P7_BufferEnable,
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I_Data => S_P7_Data,
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O_Data => O_P7_Data
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);
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end architecture; |