library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity AXI_HS_MUX is
    generic (
        G_DataWidth : integer := 8;
        G_AddressWidth : integer := 2;
        G_InBufferStages : integer := 1;
        G_OutBufferStages : integer := 1
    );
    port (
        --@ Clock signal; (**Rising edge** triggered)
        I_CLK : in std_logic;
        --@ Clock enable signal (**Active high**)
        I_CE : in std_logic;
        --@ Synchronous reset signal (**Active high**)
        I_RST : in std_logic;

        --@ @virtualbus Input @dir in Input Interface
        I_PIn_Valid : in std_logic := '0';
        O_PIn_Ready : out std_logic := '0';
        I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
        I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
        --@ @end

        --@ @virtualbus P0 @dir out P0 interface
        O_P0_Valid : out std_logic := '0';
        I_P0_Ready : in std_logic := '0';
        O_P0_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
        --@ @virtualbus P1 @dir out P1 interface
        O_P1_Valid : out std_logic := '0';
        I_P1_Ready : in std_logic := '0';
        O_P1_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
        --@ @virtualbus P2 @dir out P2 interface
        O_P2_Valid : out std_logic := '0';
        I_P2_Ready : in std_logic := '0';
        O_P2_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
        --@ @virtualbus P3 @dir out P3 interface
        O_P3_Valid : out std_logic := '0';
        I_P3_Ready : in std_logic := '0';
        O_P3_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0') --@ @end
    );
end entity AXI_HS_MUX;

architecture Rtl of AXI_HS_MUX is
    signal S_PIn_BufferEnable : std_logic := '0';

    signal S_PIn_Valid : std_logic := '0';
    signal S_PIn_Ready : std_logic := '0';

    signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');

    signal S_P0_BufferEnable : std_logic := '0';
    signal S_P0_Valid : std_logic := '0';
    signal S_P0_Ready : std_logic := '0';
    signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P1_BufferEnable : std_logic := '0';
    signal S_P1_Valid : std_logic := '0';
    signal S_P1_Ready : std_logic := '0';
    signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P2_BufferEnable : std_logic := '0';
    signal S_P2_Valid : std_logic := '0';
    signal S_P2_Ready : std_logic := '0';
    signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal S_P3_BufferEnable : std_logic := '0';
    signal S_P3_Valid : std_logic := '0';
    signal S_P3_Ready : std_logic := '0';
    signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');

begin

    I_InBufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_InBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_PIn_BufferEnable,
            I_Valid => I_PIn_Valid,
            O_Ready => O_PIn_Ready,
            O_Valid => S_PIn_Valid,
            I_Ready => S_PIn_Ready
        );

    I_InBufferData : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_PIn_BufferEnable,
            I_Data => I_PIn_Data,
            O_Data => R_PIn_Data
        );

    I_InBufferAddress : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_InBufferStages,
            G_Width => G_AddressWidth,
            G_RegisterBalancing => "forward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_PIn_BufferEnable,
            I_Data => I_PIn_Address,
            O_Data => R_PIn_Address
        );

    P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data, S_P0_Ready, S_P1_Ready, S_P2_Ready, S_P3_Ready)
    begin
        S_PIn_Ready <= '0';
        S_P0_Valid <= '0';
        S_P0_Data <= (others => '-');
        S_P1_Valid <= '0';
        S_P1_Data <= (others => '-');
        S_P2_Valid <= '0';
        S_P2_Data <= (others => '-');
        S_P3_Valid <= '0';
        S_P3_Data <= (others => '-');

        case to_integer(unsigned(R_PIn_Address)) is
            when 0 =>
                S_P0_Valid <= S_PIn_Valid;
                S_PIn_Ready <= S_P0_Ready;
                S_P0_Data <= R_PIn_Data;
            when 1 =>
                S_P1_Valid <= S_PIn_Valid;
                S_PIn_Ready <= S_P1_Ready;
                S_P1_Data <= R_PIn_Data;
            when 2 =>
                S_P2_Valid <= S_PIn_Valid;
                S_PIn_Ready <= S_P2_Ready;
                S_P2_Data <= R_PIn_Data;
            when 3 =>
                S_P3_Valid <= S_PIn_Valid;
                S_PIn_Ready <= S_P3_Ready;
                S_P3_Data <= R_PIn_Data;
            when others =>
                null;
        end case;
    end process P_MUX;

    I_P0_BufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_OutBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P0_BufferEnable,
            I_Valid => S_P0_Valid,
            O_Ready => S_P0_Ready,
            O_Valid => O_P0_Valid,
            I_Ready => I_P0_Ready
        );

    I_P0_BufferData : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P0_BufferEnable,
            I_Data => S_P0_Data,
            O_Data => O_P0_Data
        );

    I_P1_BufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_OutBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P1_BufferEnable,
            I_Valid => S_P1_Valid,
            O_Ready => S_P1_Ready,
            O_Valid => O_P1_Valid,
            I_Ready => I_P1_Ready
        );

    I_P1_BufferData : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P1_BufferEnable,
            I_Data => S_P1_Data,
            O_Data => O_P1_Data
        );

    I_P2_BufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_OutBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P2_BufferEnable,
            I_Valid => S_P2_Valid,
            O_Ready => S_P2_Ready,
            O_Valid => O_P2_Valid,
            I_Ready => I_P2_Ready
        );

    I_P2_BufferData : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P2_BufferEnable,
            I_Data => S_P2_Data,
            O_Data => O_P2_Data
        );

    I_P3_BufferCtrl : entity work.PipelineController
        generic map(
            G_PipelineStages => G_OutBufferStages
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            O_Enable => S_P3_BufferEnable,
            I_Valid => S_P3_Valid,
            O_Ready => S_P3_Ready,
            O_Valid => O_P3_Valid,
            I_Ready => I_P3_Ready
        );

    I_P3_BufferData : entity work.PipelineRegister
        generic map(
            G_PipelineStages => G_OutBufferStages,
            G_Width => G_DataWidth,
            G_RegisterBalancing => "backward"
        )
        port map(
            I_CLK => I_CLK,
            I_Enable => S_P3_BufferEnable,
            I_Data => S_P3_Data,
            O_Data => O_P3_Data
        );

end architecture;