HDL/AXI-HS-MUX
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0xMax42
2025-04-21 17:27:39 +02:00
commit 4d02a72b17
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262
AXI_HS_MUX.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_HS_MUX is
generic (
G_DataWidth : integer := 8;
G_AddressWidth : integer := 2;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus Input @dir in Input Interface
I_PIn_Valid : in std_logic := '0';
O_PIn_Ready : out std_logic := '0';
I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P0 @dir out P0 interface
O_P0_Valid : out std_logic := '0';
I_P0_Ready : in std_logic := '0';
O_P0_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P1 @dir out P1 interface
O_P1_Valid : out std_logic := '0';
I_P1_Ready : in std_logic := '0';
O_P1_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P2 @dir out P2 interface
O_P2_Valid : out std_logic := '0';
I_P2_Ready : in std_logic := '0';
O_P2_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P3 @dir out P3 interface
O_P3_Valid : out std_logic := '0';
I_P3_Ready : in std_logic := '0';
O_P3_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0') --@ @end
);
end entity AXI_HS_MUX;
architecture Rtl of AXI_HS_MUX is
signal S_PIn_BufferEnable : std_logic := '0';
signal S_PIn_Valid : std_logic := '0';
signal S_PIn_Ready : std_logic := '0';
signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
signal S_P0_BufferEnable : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_BufferEnable : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_BufferEnable : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_BufferEnable : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
begin
I_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_PIn_BufferEnable,
I_Valid => I_PIn_Valid,
O_Ready => O_PIn_Ready,
O_Valid => S_PIn_Valid,
I_Ready => S_PIn_Ready
);
I_InBufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Data,
O_Data => R_PIn_Data
);
I_InBufferAddress : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_AddressWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Address,
O_Data => R_PIn_Address
);
P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data, S_P0_Ready, S_P1_Ready, S_P2_Ready, S_P3_Ready)
begin
S_PIn_Ready <= '0';
S_P0_Valid <= '0';
S_P0_Data <= (others => '-');
S_P1_Valid <= '0';
S_P1_Data <= (others => '-');
S_P2_Valid <= '0';
S_P2_Data <= (others => '-');
S_P3_Valid <= '0';
S_P3_Data <= (others => '-');
case to_integer(unsigned(R_PIn_Address)) is
when 0 =>
S_P0_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P0_Ready;
S_P0_Data <= R_PIn_Data;
when 1 =>
S_P1_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P1_Ready;
S_P1_Data <= R_PIn_Data;
when 2 =>
S_P2_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P2_Ready;
S_P2_Data <= R_PIn_Data;
when 3 =>
S_P3_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P3_Ready;
S_P3_Data <= R_PIn_Data;
when others =>
null;
end case;
end process P_MUX;
I_P0_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_BufferEnable,
I_Valid => S_P0_Valid,
O_Ready => S_P0_Ready,
O_Valid => O_P0_Valid,
I_Ready => I_P0_Ready
);
I_P0_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_BufferEnable,
I_Data => S_P0_Data,
O_Data => O_P0_Data
);
I_P1_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_BufferEnable,
I_Valid => S_P1_Valid,
O_Ready => S_P1_Ready,
O_Valid => O_P1_Valid,
I_Ready => I_P1_Ready
);
I_P1_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_BufferEnable,
I_Data => S_P1_Data,
O_Data => O_P1_Data
);
I_P2_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_BufferEnable,
I_Valid => S_P2_Valid,
O_Ready => S_P2_Ready,
O_Valid => O_P2_Valid,
I_Ready => I_P2_Ready
);
I_P2_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_BufferEnable,
I_Data => S_P2_Data,
O_Data => O_P2_Data
);
I_P3_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_BufferEnable,
I_Valid => S_P3_Valid,
O_Ready => S_P3_Ready,
O_Valid => O_P3_Valid,
I_Ready => I_P3_Ready
);
I_P3_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_BufferEnable,
I_Data => S_P3_Data,
O_Data => O_P3_Data
);
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_HS_MUX_4 is
generic (
G_DataWidth : integer := 8;
G_AddressWidth : integer := 2;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus Input @dir in Input Interface
I_PIn_Valid : in std_logic := '0';
O_PIn_Ready : out std_logic := '0';
I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P0 @dir out P0 interface
O_P0_Valid : out std_logic := '0';
I_P0_Ready : in std_logic := '0';
O_P0_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P1 @dir out P1 interface
O_P1_Valid : out std_logic := '0';
I_P1_Ready : in std_logic := '0';
O_P1_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P2 @dir out P2 interface
O_P2_Valid : out std_logic := '0';
I_P2_Ready : in std_logic := '0';
O_P2_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P3 @dir out P3 interface
O_P3_Valid : out std_logic := '0';
I_P3_Ready : in std_logic := '0';
O_P3_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0') --@ @end
);
end entity AXI_HS_MUX_4;
architecture Rtl of AXI_HS_MUX_4 is
signal S_PIn_BufferEnable : std_logic := '0';
signal S_PIn_Valid : std_logic := '0';
signal S_PIn_Ready : std_logic := '0';
signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
signal S_P0_BufferEnable : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_BufferEnable : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_BufferEnable : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_BufferEnable : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
begin
I_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_PIn_BufferEnable,
I_Valid => I_PIn_Valid,
O_Ready => O_PIn_Ready,
O_Valid => S_PIn_Valid,
I_Ready => S_PIn_Ready
);
I_InBufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Data,
O_Data => R_PIn_Data
);
I_InBufferAddress : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_AddressWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Address,
O_Data => R_PIn_Address
);
P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data, S_P0_Ready, S_P1_Ready, S_P2_Ready, S_P3_Ready)
begin
S_PIn_Ready <= '0';
S_P0_Valid <= '0';
S_P0_Data <= (others => '-');
S_P1_Valid <= '0';
S_P1_Data <= (others => '-');
S_P2_Valid <= '0';
S_P2_Data <= (others => '-');
S_P3_Valid <= '0';
S_P3_Data <= (others => '-');
case to_integer(unsigned(R_PIn_Address)) is
when 0 =>
S_P0_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P0_Ready;
S_P0_Data <= R_PIn_Data;
when 1 =>
S_P1_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P1_Ready;
S_P1_Data <= R_PIn_Data;
when 2 =>
S_P2_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P2_Ready;
S_P2_Data <= R_PIn_Data;
when 3 =>
S_P3_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P3_Ready;
S_P3_Data <= R_PIn_Data;
when others =>
null;
end case;
end process P_MUX;
I_P0_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_BufferEnable,
I_Valid => S_P0_Valid,
O_Ready => S_P0_Ready,
O_Valid => O_P0_Valid,
I_Ready => I_P0_Ready
);
I_P0_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_BufferEnable,
I_Data => S_P0_Data,
O_Data => O_P0_Data
);
I_P1_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_BufferEnable,
I_Valid => S_P1_Valid,
O_Ready => S_P1_Ready,
O_Valid => O_P1_Valid,
I_Ready => I_P1_Ready
);
I_P1_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_BufferEnable,
I_Data => S_P1_Data,
O_Data => O_P1_Data
);
I_P2_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_BufferEnable,
I_Valid => S_P2_Valid,
O_Ready => S_P2_Ready,
O_Valid => O_P2_Valid,
I_Ready => I_P2_Ready
);
I_P2_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_BufferEnable,
I_Data => S_P2_Data,
O_Data => O_P2_Data
);
I_P3_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_BufferEnable,
I_Valid => S_P3_Valid,
O_Ready => S_P3_Ready,
O_Valid => O_P3_Valid,
I_Ready => I_P3_Ready
);
I_P3_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_BufferEnable,
I_Data => S_P3_Data,
O_Data => O_P3_Data
);
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_HS_MUX_8 is
generic (
G_DataWidth : integer := 8;
G_AddressWidth : integer := 3;
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus Input @dir in Input Interface
I_PIn_Valid : in std_logic := '0';
O_PIn_Ready : out std_logic := '0';
I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
--@ @end
--@ @virtualbus P0 @dir out P0 interface
O_P0_Valid : out std_logic := '0';
I_P0_Ready : in std_logic := '0';
O_P0_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P1 @dir out P1 interface
O_P1_Valid : out std_logic := '0';
I_P1_Ready : in std_logic := '0';
O_P1_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P2 @dir out P2 interface
O_P2_Valid : out std_logic := '0';
I_P2_Ready : in std_logic := '0';
O_P2_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P3 @dir out P3 interface
O_P3_Valid : out std_logic := '0';
I_P3_Ready : in std_logic := '0';
O_P3_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P4 @dir out P4 interface
O_P4_Valid : out std_logic := '0';
I_P4_Ready : in std_logic := '0';
O_P4_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P5 @dir out P5 interface
O_P5_Valid : out std_logic := '0';
I_P5_Ready : in std_logic := '0';
O_P5_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P6 @dir out P6 interface
O_P6_Valid : out std_logic := '0';
I_P6_Ready : in std_logic := '0';
O_P6_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'); --@ @end
--@ @virtualbus P7 @dir out P7 interface
O_P7_Valid : out std_logic := '0';
I_P7_Ready : in std_logic := '0';
O_P7_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0') --@ @end
);
end entity AXI_HS_MUX_8;
architecture Rtl of AXI_HS_MUX_8 is
signal S_PIn_BufferEnable : std_logic := '0';
signal S_PIn_Valid : std_logic := '0';
signal S_PIn_Ready : std_logic := '0';
signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
signal S_P0_BufferEnable : std_logic := '0';
signal S_P0_Valid : std_logic := '0';
signal S_P0_Ready : std_logic := '0';
signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P1_BufferEnable : std_logic := '0';
signal S_P1_Valid : std_logic := '0';
signal S_P1_Ready : std_logic := '0';
signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P2_BufferEnable : std_logic := '0';
signal S_P2_Valid : std_logic := '0';
signal S_P2_Ready : std_logic := '0';
signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P3_BufferEnable : std_logic := '0';
signal S_P3_Valid : std_logic := '0';
signal S_P3_Ready : std_logic := '0';
signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P4_BufferEnable : std_logic := '0';
signal S_P4_Valid : std_logic := '0';
signal S_P4_Ready : std_logic := '0';
signal S_P4_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P5_BufferEnable : std_logic := '0';
signal S_P5_Valid : std_logic := '0';
signal S_P5_Ready : std_logic := '0';
signal S_P5_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P6_BufferEnable : std_logic := '0';
signal S_P6_Valid : std_logic := '0';
signal S_P6_Ready : std_logic := '0';
signal S_P6_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal S_P7_BufferEnable : std_logic := '0';
signal S_P7_Valid : std_logic := '0';
signal S_P7_Ready : std_logic := '0';
signal S_P7_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
begin
I_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_PIn_BufferEnable,
I_Valid => I_PIn_Valid,
O_Ready => O_PIn_Ready,
O_Valid => S_PIn_Valid,
I_Ready => S_PIn_Ready
);
I_InBufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Data,
O_Data => R_PIn_Data
);
I_InBufferAddress : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_AddressWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Address,
O_Data => R_PIn_Address
);
P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data, S_P0_Ready, S_P1_Ready, S_P2_Ready, S_P3_Ready, S_P4_Ready, S_P5_Ready, S_P6_Ready, S_P7_Ready)
begin
S_PIn_Ready <= '0';
S_P0_Valid <= '0';
S_P0_Data <= (others => '-');
S_P1_Valid <= '0';
S_P1_Data <= (others => '-');
S_P2_Valid <= '0';
S_P2_Data <= (others => '-');
S_P3_Valid <= '0';
S_P3_Data <= (others => '-');
S_P4_Valid <= '0';
S_P4_Data <= (others => '-');
S_P5_Valid <= '0';
S_P5_Data <= (others => '-');
S_P6_Valid <= '0';
S_P6_Data <= (others => '-');
S_P7_Valid <= '0';
S_P7_Data <= (others => '-');
case to_integer(unsigned(R_PIn_Address)) is
when 0 =>
S_P0_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P0_Ready;
S_P0_Data <= R_PIn_Data;
when 1 =>
S_P1_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P1_Ready;
S_P1_Data <= R_PIn_Data;
when 2 =>
S_P2_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P2_Ready;
S_P2_Data <= R_PIn_Data;
when 3 =>
S_P3_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P3_Ready;
S_P3_Data <= R_PIn_Data;
when 4 =>
S_P4_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P4_Ready;
S_P4_Data <= R_PIn_Data;
when 5 =>
S_P5_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P5_Ready;
S_P5_Data <= R_PIn_Data;
when 6 =>
S_P6_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P6_Ready;
S_P6_Data <= R_PIn_Data;
when 7 =>
S_P7_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P7_Ready;
S_P7_Data <= R_PIn_Data;
when others =>
null;
end case;
end process P_MUX;
I_P0_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P0_BufferEnable,
I_Valid => S_P0_Valid,
O_Ready => S_P0_Ready,
O_Valid => O_P0_Valid,
I_Ready => I_P0_Ready
);
I_P0_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P0_BufferEnable,
I_Data => S_P0_Data,
O_Data => O_P0_Data
);
I_P1_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P1_BufferEnable,
I_Valid => S_P1_Valid,
O_Ready => S_P1_Ready,
O_Valid => O_P1_Valid,
I_Ready => I_P1_Ready
);
I_P1_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P1_BufferEnable,
I_Data => S_P1_Data,
O_Data => O_P1_Data
);
I_P2_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P2_BufferEnable,
I_Valid => S_P2_Valid,
O_Ready => S_P2_Ready,
O_Valid => O_P2_Valid,
I_Ready => I_P2_Ready
);
I_P2_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P2_BufferEnable,
I_Data => S_P2_Data,
O_Data => O_P2_Data
);
I_P3_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P3_BufferEnable,
I_Valid => S_P3_Valid,
O_Ready => S_P3_Ready,
O_Valid => O_P3_Valid,
I_Ready => I_P3_Ready
);
I_P3_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P3_BufferEnable,
I_Data => S_P3_Data,
O_Data => O_P3_Data
);
I_P4_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P4_BufferEnable,
I_Valid => S_P4_Valid,
O_Ready => S_P4_Ready,
O_Valid => O_P4_Valid,
I_Ready => I_P4_Ready
);
I_P4_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P4_BufferEnable,
I_Data => S_P4_Data,
O_Data => O_P4_Data
);
I_P5_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P5_BufferEnable,
I_Valid => S_P5_Valid,
O_Ready => S_P5_Ready,
O_Valid => O_P5_Valid,
I_Ready => I_P5_Ready
);
I_P5_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P5_BufferEnable,
I_Data => S_P5_Data,
O_Data => O_P5_Data
);
I_P6_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P6_BufferEnable,
I_Valid => S_P6_Valid,
O_Ready => S_P6_Ready,
O_Valid => O_P6_Valid,
I_Ready => I_P6_Ready
);
I_P6_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P6_BufferEnable,
I_Data => S_P6_Data,
O_Data => O_P6_Data
);
I_P7_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P7_BufferEnable,
I_Valid => S_P7_Valid,
O_Ready => S_P7_Ready,
O_Valid => O_P7_Valid,
I_Ready => I_P7_Ready
);
I_P7_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P7_BufferEnable,
I_Data => S_P7_Data,
O_Data => O_P7_Data
);
end architecture;

55
gen.py Normal file
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import math
import os
import argparse
from jinja2 import Environment, FileSystemLoader, TemplateError
# === Argument-Parser ===
def parse_args():
parser = argparse.ArgumentParser(
description="Generiert ein VHDL-Modul für einen AXI Handshaking Scheduler mit einer wählbaren Anzahl an Ports (nur 2^n bis max. 64 erlaubt)."
)
parser.add_argument(
"--ports", "-p",
type=int,
required=True,
help="Anzahl der Ports (z. B. 2, 4, 8, 16, 32, 64)"
)
return parser.parse_args()
# === Validierung ===
def is_power_of_two(n):
return n > 0 and (n & (n - 1)) == 0
def validate_ports(n):
if not is_power_of_two(n) or n > 64:
raise ValueError("❌ Fehler: --ports muss eine Zweierpotenz ≤ 64 sein (z. B. 2, 4, 8, 16, 32, 64).")
# === Main ===
def main():
args = parse_args()
num_ports = args.ports
validate_ports(num_ports)
TEMPLATE_DIR = "./template"
TEMPLATE_FILE = "AXI_HS_MUX_n.vhd.j2"
OUTPUT_DIR = "./build"
env = Environment(
loader=FileSystemLoader(TEMPLATE_DIR),
trim_blocks=True,
lstrip_blocks=True
)
template = env.get_template(TEMPLATE_FILE)
rendered = template.render(num_ports=num_ports)
os.makedirs(OUTPUT_DIR, exist_ok=True)
outfile = os.path.join(OUTPUT_DIR, f"AXI_HS_MUX_{num_ports}.vhdl")
with open(outfile, "w") as f:
f.write(rendered)
print(f"✔️ Generiert: {outfile}")
if __name__ == "__main__":
main()

149
template/AXI_HS_MUX_n.vhd.j2 Normal file
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{% set addr_width = (num_ports - 1).bit_length() %}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity AXI_HS_MUX_{{ num_ports }} is
generic (
G_DataWidth : integer := 8;
G_AddressWidth : integer := {{ addr_width }};
G_InBufferStages : integer := 1;
G_OutBufferStages : integer := 1
);
port (
--@ Clock signal; (**Rising edge** triggered)
I_CLK : in std_logic;
--@ Clock enable signal (**Active high**)
I_CE : in std_logic;
--@ Synchronous reset signal (**Active high**)
I_RST : in std_logic;
--@ @virtualbus Input @dir in Input Interface
I_PIn_Valid : in std_logic := '0';
O_PIn_Ready : out std_logic := '0';
I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
--@ @end
{% for i in range(num_ports) %}
--@ @virtualbus P{{ i }} @dir out P{{ i }} interface
O_P{{ i }}_Valid : out std_logic := '0';
I_P{{ i }}_Ready : in std_logic := '0';
O_P{{ i }}_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'){% if not loop.last %};{% endif %}
--@ @end
{% endfor %}
);
end entity AXI_HS_MUX_{{ num_ports }};
architecture Rtl of AXI_HS_MUX_{{ num_ports }} is
signal S_PIn_BufferEnable : std_logic := '0';
signal S_PIn_Valid : std_logic := '0';
signal S_PIn_Ready : std_logic := '0';
signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
{% for i in range(num_ports) %}
signal S_P{{ i }}_BufferEnable : std_logic := '0';
signal S_P{{ i }}_Valid : std_logic := '0';
signal S_P{{ i }}_Ready : std_logic := '0';
signal S_P{{ i }}_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
{% endfor %}
begin
I_InBufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_InBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_PIn_BufferEnable,
I_Valid => I_PIn_Valid,
O_Ready => O_PIn_Ready,
O_Valid => S_PIn_Valid,
I_Ready => S_PIn_Ready
);
I_InBufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Data,
O_Data => R_PIn_Data
);
I_InBufferAddress : entity work.PipelineRegister
generic map(
G_PipelineStages => G_InBufferStages,
G_Width => G_AddressWidth,
G_RegisterBalancing => "forward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_PIn_BufferEnable,
I_Data => I_PIn_Address,
O_Data => R_PIn_Address
);
P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data
{%- for i in range(num_ports) %}, S_P{{ i }}_Ready{% endfor %})
begin
S_PIn_Ready <= '0';
{% for i in range(num_ports) %}
S_P{{ i }}_Valid <= '0';
S_P{{ i }}_Data <= (others => '-');
{% endfor %}
case to_integer(unsigned(R_PIn_Address)) is
{% for i in range(num_ports) %}
when {{ i }} =>
S_P{{ i }}_Valid <= S_PIn_Valid;
S_PIn_Ready <= S_P{{ i }}_Ready;
S_P{{ i }}_Data <= R_PIn_Data;
{% endfor %}
when others =>
null;
end case;
end process P_MUX;
{% for i in range(num_ports) %}
I_P{{ i }}_BufferCtrl : entity work.PipelineController
generic map(
G_PipelineStages => G_OutBufferStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_Enable => S_P{{ i }}_BufferEnable,
I_Valid => S_P{{ i }}_Valid,
O_Ready => S_P{{ i }}_Ready,
O_Valid => O_P{{ i }}_Valid,
I_Ready => I_P{{ i }}_Ready
);
I_P{{ i }}_BufferData : entity work.PipelineRegister
generic map(
G_PipelineStages => G_OutBufferStages,
G_Width => G_DataWidth,
G_RegisterBalancing => "backward"
)
port map(
I_CLK => I_CLK,
I_Enable => S_P{{ i }}_BufferEnable,
I_Data => S_P{{ i }}_Data,
O_Data => O_P{{ i }}_Data
);
{% endfor %}
end architecture;