first commit

template/AXI_HS_MUX_n.vhd.j2

@@ -0,0 +1,149 @@
+{% set addr_width = (num_ports - 1).bit_length() %}
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity AXI_HS_MUX_{{ num_ports }} is
+    generic (
+        G_DataWidth : integer := 8;
+        G_AddressWidth : integer := {{ addr_width }};
+        G_InBufferStages : integer := 1;
+        G_OutBufferStages : integer := 1
+    );
+    port (
+        --@ Clock signal; (**Rising edge** triggered)
+        I_CLK : in std_logic;
+        --@ Clock enable signal (**Active high**)
+        I_CE : in std_logic;
+        --@ Synchronous reset signal (**Active high**)
+        I_RST : in std_logic;
+
+        --@ @virtualbus Input @dir in Input Interface
+        I_PIn_Valid : in std_logic := '0';
+        O_PIn_Ready : out std_logic := '0';
+        I_PIn_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
+        I_PIn_Address : in std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
+        --@ @end
+
+        {% for i in range(num_ports) %}
+        --@ @virtualbus P{{ i }} @dir out P{{ i }} interface
+        O_P{{ i }}_Valid : out std_logic := '0';
+        I_P{{ i }}_Ready : in std_logic := '0';
+        O_P{{ i }}_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0'){% if not loop.last %};{% endif %}
+        --@ @end
+        {% endfor %}
+    );
+end entity AXI_HS_MUX_{{ num_ports }};
+
+architecture Rtl of AXI_HS_MUX_{{ num_ports }} is
+    signal S_PIn_BufferEnable : std_logic := '0';
+
+    signal S_PIn_Valid : std_logic := '0';
+    signal S_PIn_Ready : std_logic := '0';
+
+    signal R_PIn_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
+    signal R_PIn_Address : std_logic_vector(G_AddressWidth - 1 downto 0) := (others => '0');
+
+    {% for i in range(num_ports) %}
+    signal S_P{{ i }}_BufferEnable : std_logic := '0';
+    signal S_P{{ i }}_Valid : std_logic := '0';
+    signal S_P{{ i }}_Ready : std_logic := '0';
+    signal S_P{{ i }}_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
+    {% endfor %}
+
+begin
+
+    I_InBufferCtrl : entity work.PipelineController
+        generic map(
+            G_PipelineStages => G_InBufferStages
+        )
+        port map(
+            I_CLK => I_CLK,
+            I_CE => I_CE,
+            I_RST => I_RST,
+            O_Enable => S_PIn_BufferEnable,
+            I_Valid => I_PIn_Valid,
+            O_Ready => O_PIn_Ready,
+            O_Valid => S_PIn_Valid,
+            I_Ready => S_PIn_Ready
+        );
+
+    I_InBufferData : entity work.PipelineRegister
+        generic map(
+            G_PipelineStages => G_InBufferStages,
+            G_Width => G_DataWidth,
+            G_RegisterBalancing => "forward"
+        )
+        port map(
+            I_CLK => I_CLK,
+            I_Enable => S_PIn_BufferEnable,
+            I_Data => I_PIn_Data,
+            O_Data => R_PIn_Data
+        );
+
+    I_InBufferAddress : entity work.PipelineRegister
+        generic map(
+            G_PipelineStages => G_InBufferStages,
+            G_Width => G_AddressWidth,
+            G_RegisterBalancing => "forward"
+        )
+        port map(
+            I_CLK => I_CLK,
+            I_Enable => S_PIn_BufferEnable,
+            I_Data => I_PIn_Address,
+            O_Data => R_PIn_Address
+        );
+
+    P_MUX : process (S_PIn_Valid, R_PIn_Address, R_PIn_Data
+        {%- for i in range(num_ports) %}, S_P{{ i }}_Ready{% endfor %})
+    begin
+        S_PIn_Ready <= '0';
+        {% for i in range(num_ports) %}
+        S_P{{ i }}_Valid <= '0';
+        S_P{{ i }}_Data <= (others => '-');
+        {% endfor %}
+
+        case to_integer(unsigned(R_PIn_Address)) is
+                {% for i in range(num_ports) %}
+            when {{ i }} =>
+                S_P{{ i }}_Valid <= S_PIn_Valid;
+                S_PIn_Ready <= S_P{{ i }}_Ready;
+                S_P{{ i }}_Data <= R_PIn_Data;
+                {% endfor %}
+            when others =>
+                null;
+        end case;
+    end process P_MUX;
+
+    {% for i in range(num_ports) %}
+    I_P{{ i }}_BufferCtrl : entity work.PipelineController
+    generic map(
+        G_PipelineStages => G_OutBufferStages
+    )
+    port map(
+        I_CLK => I_CLK,
+        I_CE => I_CE,
+        I_RST => I_RST,
+        O_Enable => S_P{{ i }}_BufferEnable,
+        I_Valid => S_P{{ i }}_Valid,
+        O_Ready => S_P{{ i }}_Ready,
+        O_Valid => O_P{{ i }}_Valid,
+        I_Ready => I_P{{ i }}_Ready
+    );
+
+    I_P{{ i }}_BufferData : entity work.PipelineRegister
+    generic map(
+        G_PipelineStages => G_OutBufferStages,
+        G_Width => G_DataWidth,
+        G_RegisterBalancing => "backward"
+    )
+    port map(
+        I_CLK => I_CLK,
+        I_Enable => S_P{{ i }}_BufferEnable,
+        I_Data => S_P{{ i }}_Data,
+        O_Data => O_P{{ i }}_Data
+    );
+
+    {% endfor %}
+end architecture;